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ICE_TEA_BIOS/Board/Oem/L05AlderLakePMultiBoardPkg/ME/16.0.10.1434/S570.xml
LCFC\AiXia.Jiang a870bff2f4 1.Frist commit
2022-09-30 14:59:06 +08:00

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<?xml version="1.0" ?>
<FitData version="" layout_name="Intel(R) AlderLake P Chipset - Consumer - SPI">
<BuildSettings label="Build Settings">
<BuildResults label="Build Results">
<MeuToolPath value="" label="Intel(R) Manifest Extension Utility Path" help_text="" key="ManifestSigningUtilPlugin:SigningContainer:MeuToolPath"/>
<OpenSSLToolPath value="" label="Open SSL Signing Tool Path" help_text="" key="ManifestSigningUtilPlugin:SigningContainer:OpenSSLToolPath"/>
<SigningEnabled value="Disabled" value_list="['Disabled', 'Enabled']" label="Signing Enabled" help_text="" key="ManifestSigningUtilPlugin:SigningContainer:SigningEnabled"/>
<DescSigningKey value="" label="Descriptor Debug Signing Key" help_text="This is the path to the private debug key used to sign the Descriptor, while public key hash of it is included in the OEM hash manifest. This setting is operative only when Flash Descriptor Verification is enabled (See DescConfiguration/FdvEnabled)." key="DescriptorPlugin:FdvManifest:DescSigningKey"/>
<Sku value="No Emulation" value_list="['No Emulation', 'Premium', 'ADP M Premium']" label="Sku" help_text="SKU Emulation" key="CsePlugin:HVMP:hvmp_sku"/>
<DataRestoreStatus value="Disabled" value_list="['Disabled', 'Enabled']" label="Factory Defaults Restoration Status" help_text="Enable data restore to manufacturing defaults" key="CsePlugin:FDCR:DataRestoreStatus"/>
<RegionOrder value="53241" label="Region Order" help_text="1=BiosRegion, 2=CseRegion, 3=GbeRegion, 4=PdrRegion, 5=EcRegion" key="GlobalData:ImageInfoDataBucket:RegionOrder"/>
<BuildOutputFilename value="$DestDir$\image.bin" label="Output Path" help_text="Name of the output binary file. In case of multiple binaries, their names will be exactly as the name of the first binary with a suffix number, for example: image.bin (1st binary) ,image1.bin, image2.bin etc." key="GlobalData:ImageInfoDataBucket:BuildOutputFilename"/>
<OutputConfigXmlFileName value="$DestDir$\Untitled.xml" label="Output Config XML Path" help_text="" key="GlobalData:ImageInfoDataBucket:OutputConfigXmlFileName"/>
<NumberOfFlashComponents value="2" label="Number of Flash Components" help_text="Number of output binaries. In case of multiple binaries, their names will be exactly as the name of the first binary with a suffix number, for example: image.bin (1st binary) ,image1.bin, image2.bin etc." key="GlobalData:ImageInfoDataBucket:NumberOfFlashComponents"/>
<FlashComponentsSizes value="8,16" label="Flash Components Sizes" help_text="Size of each output binary, the values should be separated by ',' (comma). For example if Number of Flash Components is 2 then a possible value would be '32,8'. Use NA to build without size restriction and set NumberOfFlashComponents to 1." key="GlobalData:ImageInfoDataBucket:FlashComponentsSizes"/>
<FlashComponentsSizesUnit value="MB" value_list="['Bytes', 'KB', 'MB', 'GB']" label="Flash Components Sizes Unit" help_text="Units for output binaries sizes" key="GlobalData:ImageInfoDataBucket:FlashComponentsSizesUnit"/>
<IfwiRedundancyEnabled value="false" value_list="['false', 'true']" label="Redundancy Enabled" help_text="Enable Redundancy support for critical layout components" key="GlobalData:ImageInfoDataBucket:IfwiRedundancyEnabled"/>
<IfwiBuildVersion value="0x0" label="Ifwi Image Version" help_text="32-bit value to use as the IFWI build version number" key="GlobalData:ImageInfoDataBucket:IfwiBuildVersion"/>
</BuildResults>
<HarnessGlobalData label="Harness Global Data">
<HarnessProject value="ADP-P PCH (w/ADL-P / M CPU) RDL v1.0.2.5" label="Harness Project" help_text="" key="DescriptorPlugin:HarnessGlobalData:HarnessProject"/>
<HarnessLabel value="v0.94 ADP-P (Harness #16)" label="Harness Label" help_text="" key="DescriptorPlugin:HarnessGlobalData:HarnessLabel"/>
<HarnessRevision value="#16" label="Harness Revision" help_text="" key="DescriptorPlugin:HarnessGlobalData:HarnessRevision"/>
<SelectedRvp value="ADL-P DDR4 (ADL-P + ADP-P)" value_list="['HFPGA', 'Simics', 'SLE', 'ADL-P LP4x (ADL-P + ADP-P)', 'ADL-P DDR5 (ADL-P + ADP-P)', 'ADL-P LP5 (ADL-P + ADP-P)', 'ADL-P DDR4 (ADL-P + ADP-P)', 'ADL-P MR DDR5 (ADL-P + ADP-P)', 'ADL-M LP4x RVP1 (ADL-M + ADP-P)', 'ADL-M LP5 RVP2 (ADL-M + ADP-P)', 'ADL-M LP5 RVP3 (ADL-M + ADP-P)', 'ADL-P GCS (ADL-P + ADP-P)']" label="Selected RVP" help_text="Specify platform RVP for getting Soft Straps default values." key="DescriptorPlugin:HarnessGlobalData:SelectedRvp"/>
</HarnessGlobalData>
<PathVars label="Path Vars">
<WorkingDir value="." label="$WorkingDir$" help_text="Path for environment variable $WorkingDir$" key="GlobalData:EnvironmentVariablesDataBucket:WorkingDir"/>
<SourceDir value="." label="$SourceDir$" help_text="Path for environment variable $SourceDir$" key="GlobalData:EnvironmentVariablesDataBucket:SourceDir"/>
<DestDir value="." label="$DestDir$" help_text="Path for environment variable $DestDir$" key="GlobalData:EnvironmentVariablesDataBucket:DestDir"/>
<UserVar1 value="." label="$UserVar1$" help_text="Path for environment variable $UserVar1$" key="GlobalData:EnvironmentVariablesDataBucket:UserVar1"/>
<UserVar2 value="." label="$UserVar2$" help_text="Path for environment variable $UserVar2$" key="GlobalData:EnvironmentVariablesDataBucket:UserVar2"/>
<UserVar3 value="." label="$UserVar3$" help_text="Path for environment variable $UserVar3$" key="GlobalData:EnvironmentVariablesDataBucket:UserVar3"/>
</PathVars>
</BuildSettings>
<FlashLayout label="Flash Layout">
<DescriptorRegion label="Descriptor Region">
<OemBinary value="" label="OEM Section Binary" help_text="This loads the OEM Section binary that will be merged into the output image generated by the Intel(R) FIT tool." key="DescriptorPlugin:OEM:input_file_path"/>
</DescriptorRegion>
<BiosRegion label="BIOS Region">
<InputFile value="../../BIOS/AlderLakeP.fd" label="BIOS Binary File" help_text="This loads the BIOS binary that will be merged into the output image generated by the Intel (R) FIT tool." key="BiosPlugin:BiosRegion:input_file_path"/>
<Length value="0x0" label="BIOS Length" help_text="" key="BiosPlugin:BiosRegion:length"/>
</BiosRegion>
<Ifwi_IntelMePmcRegion label="Ifwi: Intel(R) Me and Pmc Region">
<MeRegionFile value="CSME/Silicon/P/CSME_A0_Consumer_16.0.10.1434_preprod.bin" label="Intel(R) ME Binary File" help_text="This loads the Intel(R) ME binary that will be merged into the output image generated by the Intel(R) FIT tool." key="CsePlugin:CseRegion:MeRegionFile"/>
<Length value="0x0" label="Length" help_text="" key="CsePlugin:CseRegion:Length"/>
<PmcBinary value="PMC/PMC_160.01.00.1011_preprod.bin" label="PMC Binary File" help_text="This loads the PMC binary that will be merged into the output image generated by Intel(R) FIT tool." key="CsePlugin:PMC:PmcBinary_path"/>
<ChipInitBinary value="CSME_A0_Consumer_16.0.10.1434_preprod/NVARS#MphyTable#ChipInitBinary.bin" label="Chipset Initialization Binary" help_text="This loads the Chipset Initialization binary that will be merged into the output image generated by the Intel(R) FIT tool." key="CsePlugin:ChipsetInit:MphyTable#ChipInitBinary"/>
<ResizeNftpForFtpr value="Enabled" value_list="['Disabled', 'Enabled']" label="Enables NFTP resize for FTPR loading" help_text="Used to enable NFTP resize for FTPR loading to perform FWU process. Disable for SKU's and platforms with limited image size, without FWU support only." key="CsePlugin:NFTP:ResizeNftpForFtpr"/>
</Ifwi_IntelMePmcRegion>
<EcRegion label="EC Region">
<EcRegionPointer value="" label="EC Region Pointer File" help_text="This loads a binary containing the 16 byte value to be written in the Embedded Controller Pointer region." key="DescriptorPlugin:EcRegionPointer:input_file_path"/>
<InputFile value="" label="EC Binary File" help_text="This loads the Embedded Controller binary used for eSPI that will be merged into the output image generated by the Intel (R) FIT tool." key="EcPlugin:EcRegion:input_file_path"/>
<Enabled value="Disabled" value_list="['Disabled', 'Enabled']" label="EC Region Enable" help_text="This option allows the user to enable or disable the Embedded Controller Data Region." key="EcPlugin:EcRegion:enabled"/>
<Length value="0x0" label="EC Length" help_text="" key="EcPlugin:EcRegion:length"/>
</EcRegion>
<GbeRegion label="GbE Region">
<InputFile value="" label="GbE Binary File" help_text="This loads the Intel(R) Integrated LAN binary that will be merged into the output image generated by the Intel (R) FIT tool." key="GbePlugin:GbeRegion:input_file_path"/>
<Enabled value="Disabled" value_list="['Disabled', 'Enabled']" label="GbE Region Enable" help_text="This option allows the user to enable or disable the GbE Region" key="GbePlugin:GbeRegion:enabled"/>
<Length value="0x0" label="GbE Length" help_text="" key="GbePlugin:GbeRegion:length"/>
</GbeRegion>
<PdrRegion label="PDR Region">
<InputFile value="" label="PDR Binary File" help_text="This loads the Platform Data region binary that will be merged into the output image generated by the Intel (R) FIT tool." key="PdrPlugin:PdrRegion:input_file_path"/>
<Enabled value="Disabled" value_list="['Disabled', 'Enabled']" label="PDR Region Enable" help_text="This option allows the user to enable or disable the Platform Data Region." key="PdrPlugin:PdrRegion:enabled"/>
<Length value="0x0" label="PDR Length" help_text="" key="PdrPlugin:PdrRegion:length"/>
</PdrRegion>
<SubPartitions label="Sub Partitions">
<IunitSubPartition label="IUnit Sub-Partition">
<InputFile value="" label="IUnit Binary File" help_text="This loads the IUnit binary that will be merged into the output image generated by Intel(R) FIT tool." key="CsePlugin:IUNIT:InputFile_path"/>
</IunitSubPartition>
<PchcSubPartitionData label="PCH Configuration Sub-Partition">
<InputFile value="PCHC/PCHC_16.0.0.1008_preprod.bin" label="PCH Configuration File" help_text="This loads the PCH Configuration binary that will be merged into the output image generated by Intel(R) FIT tool." key="CsePlugin:PCHC:InputFile_path"/>
</PchcSubPartitionData>
<GbstSubPartitionData label="GBST Configuration Sub-Partition">
<InputFile value="" label="GBST Configuration File" help_text="This loads the GBST Configuration binary that will be merged into the output image generated by Intel(R) FIT tool." key="CsePlugin:GBST:InputFile_path"/>
</GbstSubPartitionData>
</SubPartitions>
</FlashLayout>
<FlashSettings label="Flash Settings">
<FlashComponents label="Flash Components">
<SpiResHldDelay value="8us" value_list="['0us', '2us', '4us', '6us', '8us', '10us', '12us', '14us']" label="SPI Resume Hold-off Delay" help_text="Specifies the time after the completion of a pri_op before the flash controller sends the resume instruction. If a new pri_op is eligible &lt;br /&gt;to be issued prior to the end of this delay time then the pri_op is issued and the timer is reinitialized to tRHD. 3-bit field encodes count &lt;br /&gt;with range 0-7. tRHD = count * 2us." key="DescriptorPlugin:PchStraps:PCH_Strap_SPI_spi_resume_holdoff_delay"/>
<SpiSusResEn value="Yes" value_list="['Yes', 'No']" label="SPI Suspend / Resume Enabled" help_text="When this setting is enabled writes and erases may be suspended to allow a read to be issued on the flash device. When this setting is &lt;br /&gt;disabled no transaction will be allowed to the busy flash device." key="DescriptorPlugin:PchStraps:PCH_Strap_SPI_spi_suspend_resume_disable"/>
<SpiOooEnable value="Yes" value_list="['Yes', 'No']" label="SPI Out of Order operation Enabled" help_text="When this setting is enabled priority operations may be issued while waiting for write / erase operations to complete on the flash device. &lt;br /&gt;When this setting is disabled all write / erase type operations in order." key="DescriptorPlugin:PchStraps:PCH_Strap_SPI_spi_ooo_disable"/>
<SpiMxWrErResSusInt value="No Ceiling" value_list="['128us', '256us', '512us', 'No Ceiling']" label="SPI Max write / erase Resume to Suspend intervals" help_text="This setting specifies the maximum value for the write and erase Resume to Suspend intervals." key="DescriptorPlugin:PchStraps:PCH_Strap_SPI_spi_resume_to_suspend_ceiling"/>
<SpiIdlDpdwntimeout value="0x5" label="SPI Idle to Deep Power Down Timeout" help_text="SPI Idle to Deep Power Down Timeout Default Specifies the time in microseconds that the Flash Controller waits after all activity is idle before commanding the flash devices to Deep Power down, time = 2^N microseconds." key="DescriptorPlugin:PchStraps:PCH_Strap_SPI_SPI_IDLE_DEEP_PWRDN_DEFAULT_TIME"/>
<SpiGblProtRng value="0x0" label="SPI Global Protected Range" help_text="Sets the default value of the Global Protected Range register in the SPI Flash Controller." key="DescriptorPlugin:PchStraps:PCH_Strap_SPI_GLOBAL_PROTECTED_RNG_DEF"/>
<SoftReBindEnable value="No" value_list="['No', 'Yes']" label="Software Re-Binding Enabled" help_text="When enabled this settings will allow for SPI re-binding to a new PCH during manufacturing and remanufacturing flows prior to platform EOM. &lt;br /&gt; &lt;br /&gt;Note: Re-binding to a replacement PCH can only be done a maximum of 5 times before the SPI part needs to be re-flashed." key="DescriptorPlugin:PchStraps:PCH_Strap_CSME_CSE_SW_BIND_EN"/>
</FlashComponents>
<HostCpuBiosMasterAccess label="Host CPU / BIOS Master Access">
<HostCpuWriteAccessIntelRecommended value="0xFFFF" value_list="['0xFFFF', '0x011A', '0x000A', '0x010A', '0x001A', 'Custom']" label="Host CPU / BIOS Write Access Intel Recommended" help_text="This setting determines Host CPU / BIOS write access to the other regions. Note: If pre-locking is not set, closemnf will revert back master access settings to 'golden master access settings'. For further details on Region Access Control see the SPI Programming guide." key="DescriptorPlugin:MasterAccessPermissions:host_cpu_write_access_intel_recommended"/>
<HostCpuWriteAccessCustom value="0x0" label="Host CPU / BIOS Write Access Custom" help_text="This setting determines Host CPU / BIOS write access to the other regions. Note: If pre-locking is not set, closemnf will revert back master access settings to 'golden master access settings'. For further details on Region Access Control see the SPI Programming guide." key="DescriptorPlugin:MasterAccessPermissions:host_cpu_write_access_custom"/>
<HostCpuReadAccessIntelRecommended value="0xFFFF" value_list="['0xFFFF', '0x000F', '0x010F', '0x001F', '0x011F', 'Custom']" label="Host CPU / BIOS Read Access Intel Recommended" help_text="This setting determines Host CPU / BIOS read access to the other regions. Note: If pre-locking is not set, closemnf will revert back master access settings to 'golden master access settings'. For further details on Region Access Control see the SPI Programming guide." key="DescriptorPlugin:MasterAccessPermissions:host_cpu_read_access_intel_recommended"/>
<HostCpuReadAccessCustom value="0x0" label="Host CPU / BIOS Read Access Custom" help_text="This setting determines Host CPU / BIOS read access to the other regions. Note: If pre-locking is not set, closemnf will revert back master access settings to 'golden master access settings'. For further details on Region Access Control see the SPI Programming guide." key="DescriptorPlugin:MasterAccessPermissions:host_cpu_read_access_custom"/>
</HostCpuBiosMasterAccess>
<IntelMeMasterAccess label="Intel(R) ME Master Access">
<MeWriteAccessIntelRecommended value="0xFFFF" value_list="['0xFFFF', '0x0004', 'Custom']" label="Intel(R) ME Write Access Intel Recommended" help_text="This setting determines ME write access to the other regions. Note: If pre-locking is not set, closemnf will revert back master access settings to 'golden master access settings'. For further details on Region Access Control see SPI Programming guide." key="DescriptorPlugin:MasterAccessPermissions:me_write_access_intel_recommended"/>
<MeWriteAccessCustom value="0x0" label="Intel(R) ME Write Access Custom" help_text="This setting determines ME write access to the other regions. Note: If pre-locking is not set, closemnf will revert back master access settings to 'golden master access settings'. For further details on Region Access Control see SPI Programming guide." key="DescriptorPlugin:MasterAccessPermissions:me_write_access_custom"/>
<MeReadAccessIntelRecommended value="0xFFFF" value_list="['0xFFFF', '0x000D', 'Custom']" label="Intel(R) ME Read Access Intel Recommended" help_text="This setting determines ME read access to the other regions. Note: If pre-locking is not set, closemnf will revert back master access settings to 'golden master access settings'. For further details on Region Access Control see SPI Programming guide." key="DescriptorPlugin:MasterAccessPermissions:me_read_access_intel_recommended"/>
<MeReadAccessCustom value="0x0" label="Intel(R) ME Read Access Custom" help_text="This setting determines ME read access to the other regions. Note: If pre-locking is not set, closemnf will revert back master access settings to 'golden master access settings'. For further details on Region Access Control see SPI Programming guide." key="DescriptorPlugin:MasterAccessPermissions:me_read_access_custom"/>
</IntelMeMasterAccess>
<GbeMasterAccess label="GbE Master Access">
<GbeWriteAccessIntelRecommended value="0xFFFF" value_list="['0xFFFF', '0x0008', 'Custom']" label="GbE Write Access Intel Recommended" help_text="This setting determines GBE region write access to the other regions. Note: If pre-locking is not set, closemnf will revert back master access settings to 'golden master access settings'. For further details on Region Access Control see SPI Programming guide." key="DescriptorPlugin:MasterAccessPermissions:gbe_write_access_intel_recommended"/>
<GbeWriteAccessCustom value="0x0" label="GbE Write Access Custom" help_text="This setting determines GBE region write access to the other regions. Note: If pre-locking is not set, closemnf will revert back master access settings to 'golden master access settings'. For further details on Region Access Control see SPI Programming guide." key="DescriptorPlugin:MasterAccessPermissions:gbe_write_access_custom"/>
<GbeReadAccessIntelRecommended value="0xFFFF" value_list="['0xFFFF', '0x0009', 'Custom']" label="GbE Read Access Intel Recommended" help_text="This setting determines GBE region read access to the other regions. Note: If pre-locking is not set, closemnf will revert back master access settings to 'golden master access settings'. For further details on Region Access Control see SPI Programming guide." key="DescriptorPlugin:MasterAccessPermissions:gbe_read_access_intel_recommended"/>
<GbeReadAccessCustom value="0x0" label="GbE Read Access Custom" help_text="This setting determines GBE region read access to the other regions. Note: If pre-locking is not set, closemnf will revert back master access settings to 'golden master access settings'. For further details on Region Access Control see SPI Programming guide." key="DescriptorPlugin:MasterAccessPermissions:gbe_read_access_custom"/>
</GbeMasterAccess>
<EcMasterAccess label="EC Master Access">
<EcWriteAccessIntelRecommended value="0xFFFF" value_list="['0xFFFF', '0x0100', 'Custom']" label="Embedded Controller Write Access Intel Recommended" help_text="This setting determines Embedded Controller region write access to the other regions. Note: If pre-locking is not set, closemnf will revert back master access settings to 'golden master access settings'. For further details on Region Access Control see SPI Programming guide." key="DescriptorPlugin:MasterAccessPermissions:ec_write_access_intel_recommended"/>
<EcWriteAccessCustom value="0x0" label="Embedded Controller Write Access Custom" help_text="This setting determines Embedded Controller region write access to the other regions. Note: If pre-locking is not set, closemnf will revert back master access settings to 'golden master access settings'. For further details on Region Access Control see SPI Programming guide." key="DescriptorPlugin:MasterAccessPermissions:ec_write_access_custom"/>
<EcReadAccessIntelRecommended value="0xFFFF" value_list="['0xFFFF', '0x0101', '0x0103', 'Custom']" label="Embedded Controller Read Access Intel Recommended" help_text="This setting determines Embedded Controller region read access to the other regions. Note: If pre-locking is not set, closemnf will revert back master access settings to 'golden master access settings'. For further details on Region Access Control see SPI Programming guide." key="DescriptorPlugin:MasterAccessPermissions:ec_read_access_intel_recommended"/>
<EcReadAccessCustom value="0x0" label="Embedded Controller Read Access Custom" help_text="This setting determines Embedded Controller region read access to the other regions. Note: If pre-locking is not set, closemnf will revert back master access settings to 'golden master access settings'. For further details on Region Access Control see SPI Programming guide." key="DescriptorPlugin:MasterAccessPermissions:ec_read_access_custom"/>
</EcMasterAccess>
<FlashConfiguration label="Flash Configuration">
<SpiDualOutReadEnable value="Yes" value_list="['No', 'Yes']" label="Dual I/O Read Enable" help_text="This soft-strap only has effect if Dual I/O Read is discovered as supported via the SFDP." key="DescriptorPlugin:FLCOMP:spi_dual_out_read_enable"/>
<SpiDualIoReadEnable value="Yes" value_list="['No', 'Yes']" label="Dual Output Read Enable" help_text="This soft-strap only has effect if Dual I/O Read is discovered as supported via the SFDP." key="DescriptorPlugin:FLCOMP:spi_dual_io_read_enable"/>
<QuadOutReadEnable value="Yes" value_list="['No', 'Yes']" label="Quad Output Read Enable" help_text="This soft-strap only has effect if Quad Output Read is discovered as supported via the SFDP." key="DescriptorPlugin:FLCOMP:quad_out_read_enable"/>
<QuadIoReadEnable value="Yes" value_list="['No', 'Yes']" label="Quad I/O Read Enable" help_text="This soft-strap only has effect if Quad I/O Read is discovered as supported via the SFDP." key="DescriptorPlugin:FLCOMP:quad_io_read_enable"/>
<FastReadSupport value="Yes" value_list="['No', 'Yes']" label="Fast Read Supported" help_text="This setting allows customers to enable support for Fast Read capabilities for flash components. See SPI and SMIP Programming guide further details. Note: This setting needs to be enabled when using Dual / Quad enabled components." key="DescriptorPlugin:FLCOMP:fast_read_support"/>
<FastReadClockFreq value="50MHz" value_list="['100MHz', '50MHz', '33MHz', '25MHz', '14MHz']" label="Fast Read Clock Frequency" help_text="This setting allows customers to configure the flash component clock frequency setting for Fast Read. See SPI Programming guide further details." key="DescriptorPlugin:FLCOMP:fast_read_clock_freq"/>
<WriteEraseClockFreq value="50MHz" value_list="['100MHz', '50MHz', '33MHz', '25MHz', '14MHz']" label="Write and Erase Clock Frequency" help_text="This setting allows customers to configure the flash component clock frequency setting for Write and Erase. See SPI Programming guide further details." key="DescriptorPlugin:FLCOMP:write_erase_clock_freq"/>
<ReadIdAndReadStatClkFreq value="50MHz" value_list="['100MHz', '50MHz', '33MHz', '25MHz', '14MHz']" label="Read ID and Read Status Clock Frequency" help_text="This setting allows customers to configure the flash component clock frequency setting for Read ID and Read Status. See SPI Programming guide further details." key="DescriptorPlugin:FLCOMP:read_id_and_read_stat_clk_freq"/>
<InvalidInstruction0 value="0x21" label="Invalid Instruction 0" help_text="This setting allows customers to configure invalid instruction to protect against Chip Erase. Note: This setting should be set to '0' if there are not Invalid instructions." key="DescriptorPlugin:FLIL:invalid_instruction_0"/>
<InvalidInstruction1 value="0x42" label="Invalid Instruction 1" help_text="This setting allows customers to configure invalid instruction to protect against Chip Erase. Note: This setting should be set to '0' if there are not Invalid instructions." key="DescriptorPlugin:FLIL:invalid_instruction_1"/>
<InvalidInstruction2 value="0x60" label="Invalid Instruction 2" help_text="This setting allows customers to configure invalid instruction to protect against Chip Erase. Note: This setting should be set to '0' if there are not Invalid instructions." key="DescriptorPlugin:FLIL:invalid_instruction_2"/>
<InvalidInstruction3 value="0xAD" label="Invalid Instruction 3" help_text="This setting allows customers to configure invalid instruction to protect against Chip Erase. Note: This setting should be set to '0' if there are not Invalid instructions." key="DescriptorPlugin:FLIL:invalid_instruction_3"/>
<InvalidInstruction4 value="0xB7" label="Invalid Instruction 4" help_text="This setting allows customers to configure invalid instruction to protect against Chip Erase. Note: This setting should be set to '0' if there are not Invalid instructions." key="DescriptorPlugin:FLIL:invalid_instruction_4"/>
<InvalidInstruction5 value="0xB9" label="Invalid Instruction 5" help_text="This setting allows customers to configure invalid instruction to protect against Chip Erase. Note: This setting should be set to '0' if there are not Invalid instructions." key="DescriptorPlugin:FLIL:invalid_instruction_5"/>
<InvalidInstruction6 value="0xC4" label="Invalid Instruction 6" help_text="This setting allows customers to configure invalid instruction to protect against Chip Erase. Note: This setting should be set to '0' if there are not Invalid instructions." key="DescriptorPlugin:FLIL:invalid_instruction_6"/>
<InvalidInstruction7 value="0xC7" label="Invalid Instruction 7" help_text="This setting allows customers to configure invalid instruction to protect against Chip Erase. Note: This setting should be set to '0' if there are not Invalid instructions." key="DescriptorPlugin:FLIL:invalid_instruction_7"/>
</FlashConfiguration>
<VsccTable label="VSCC Table">
<VsccEntries label="VSCC Entries">
<VsccEntry label="VSCC Entry">
<VsccEntryActive value="false" value_list="['false', 'true']" label="Active" help_text="" key="DescriptorPlugin:VsccTable:0/VsccEntryActive"/>
<VsccEntryName value="ATF26DF321" label="Part Name" help_text="This setting allow the OEM input a name designation for each flash component being used. Note: This is a free form entry field it does not affect actual flash component operation." key="DescriptorPlugin:VsccTable:0/VsccEntryName"/>
<VsccEntryVendorId value="0x1F" label="Vendor ID" help_text="This configures the JEDEC vendor specific byte ID of the SPI flash &amp;lt;br /&amp;gt;Component see Canonlake H / LP SPI Programming guide for further details." key="DescriptorPlugin:VsccTable:0/VsccEntryVendorId"/>
<VsccEntryDeviceId0 value="0x47" label="Device ID 0" help_text="This configures the JEDEC device specific byte ID 0 of the SPI flash Component see Canonlake H / LP SPI Programming guide for further details." key="DescriptorPlugin:VsccTable:0/VsccEntryDeviceId0"/>
<VsccEntryDeviceId1 value="0x0" label="Device ID 1" help_text="This configures the JEDEC device specific byte ID 1 of the SPI flash Component see Canonlake H / LP SPI Programming guide for further details." key="DescriptorPlugin:VsccTable:0/VsccEntryDeviceId1"/>
</VsccEntry>
<VsccEntry label="VSCC Entry">
<VsccEntryActive value="true" value_list="['false', 'true']" label="Active" help_text="" key="DescriptorPlugin:VsccTable:1/VsccEntryActive"/>
<VsccEntryName value="W25Q128JV" label="Part Name" help_text="This setting allow the OEM input a name designation for each flash component being used. Note: This is a free form entry field it does not affect actual flash component operation." key="DescriptorPlugin:VsccTable:1/VsccEntryName"/>
<VsccEntryVendorId value="0xEF" label="Vendor ID" help_text="This configures the JEDEC vendor specific byte ID of the SPI flash &amp;lt;br /&amp;gt;Component see Canonlake H / LP SPI Programming guide for further details." key="DescriptorPlugin:VsccTable:1/VsccEntryVendorId"/>
<VsccEntryDeviceId0 value="0x40" label="Device ID 0" help_text="This configures the JEDEC device specific byte ID 0 of the SPI flash Component see Canonlake H / LP SPI Programming guide for further details." key="DescriptorPlugin:VsccTable:1/VsccEntryDeviceId0"/>
<VsccEntryDeviceId1 value="0x18" label="Device ID 1" help_text="This configures the JEDEC device specific byte ID 1 of the SPI flash Component see Canonlake H / LP SPI Programming guide for further details." key="DescriptorPlugin:VsccTable:1/VsccEntryDeviceId1"/>
</VsccEntry>
<VsccEntry label="VSCC Entry">
<VsccEntryActive value="true" value_list="['false', 'true']" label="Active" help_text="" key="DescriptorPlugin:VsccTable:2/VsccEntryActive"/>
<VsccEntryName value="W25Q64JV" label="Part Name" help_text="This setting allow the OEM input a name designation for each flash component being used. Note: This is a free form entry field it does not affect actual flash component operation." key="DescriptorPlugin:VsccTable:2/VsccEntryName"/>
<VsccEntryVendorId value="0xEF" label="Vendor ID" help_text="This configures the JEDEC vendor specific byte ID of the SPI flash &amp;lt;br /&amp;gt;Component see Canonlake H / LP SPI Programming guide for further details." key="DescriptorPlugin:VsccTable:2/VsccEntryVendorId"/>
<VsccEntryDeviceId0 value="0x40" label="Device ID 0" help_text="This configures the JEDEC device specific byte ID 0 of the SPI flash Component see Canonlake H / LP SPI Programming guide for further details." key="DescriptorPlugin:VsccTable:2/VsccEntryDeviceId0"/>
<VsccEntryDeviceId1 value="0x17" label="Device ID 1" help_text="This configures the JEDEC device specific byte ID 1 of the SPI flash Component see Canonlake H / LP SPI Programming guide for further details." key="DescriptorPlugin:VsccTable:2/VsccEntryDeviceId1"/>
</VsccEntry>
<VsccEntry label="VSCC Entry">
<VsccEntryActive value="true" value_list="['false', 'true']" label="Active" help_text="" key="DescriptorPlugin:VsccTable:3/VsccEntryActive"/>
<VsccEntryName value="MX25L12872F" label="Part Name" help_text="This setting allow the OEM input a name designation for each flash component being used. Note: This is a free form entry field it does not affect actual flash component operation." key="DescriptorPlugin:VsccTable:3/VsccEntryName"/>
<VsccEntryVendorId value="0xC2" label="Vendor ID" help_text="This configures the JEDEC vendor specific byte ID of the SPI flash &amp;lt;br /&amp;gt;Component see Canonlake H / LP SPI Programming guide for further details." key="DescriptorPlugin:VsccTable:3/VsccEntryVendorId"/>
<VsccEntryDeviceId0 value="0x20" label="Device ID 0" help_text="This configures the JEDEC device specific byte ID 0 of the SPI flash Component see Canonlake H / LP SPI Programming guide for further details." key="DescriptorPlugin:VsccTable:3/VsccEntryDeviceId0"/>
<VsccEntryDeviceId1 value="0x18" label="Device ID 1" help_text="This configures the JEDEC device specific byte ID 1 of the SPI flash Component see Canonlake H / LP SPI Programming guide for further details." key="DescriptorPlugin:VsccTable:3/VsccEntryDeviceId1"/>
</VsccEntry>
<VsccEntry label="VSCC Entry">
<VsccEntryActive value="true" value_list="['false', 'true']" label="Active" help_text="" key="DescriptorPlugin:VsccTable:4/VsccEntryActive"/>
<VsccEntryName value="MX77L6450F" label="Part Name" help_text="This setting allow the OEM input a name designation for each flash component being used. Note: This is a free form entry field it does not affect actual flash component operation." key="DescriptorPlugin:VsccTable:4/VsccEntryName"/>
<VsccEntryVendorId value="0xC2" label="Vendor ID" help_text="This configures the JEDEC vendor specific byte ID of the SPI flash &amp;lt;br /&amp;gt;Component see Canonlake H / LP SPI Programming guide for further details." key="DescriptorPlugin:VsccTable:4/VsccEntryVendorId"/>
<VsccEntryDeviceId0 value="0x75" label="Device ID 0" help_text="This configures the JEDEC device specific byte ID 0 of the SPI flash Component see Canonlake H / LP SPI Programming guide for further details." key="DescriptorPlugin:VsccTable:4/VsccEntryDeviceId0"/>
<VsccEntryDeviceId1 value="0x17" label="Device ID 1" help_text="This configures the JEDEC device specific byte ID 1 of the SPI flash Component see Canonlake H / LP SPI Programming guide for further details." key="DescriptorPlugin:VsccTable:4/VsccEntryDeviceId1"/>
</VsccEntry>
<VsccEntry label="VSCC Entry">
<VsccEntryActive value="true" value_list="['false', 'true']" label="Active" help_text="" key="DescriptorPlugin:VsccTable:5/VsccEntryActive"/>
<VsccEntryName value="GD25B127D" label="Part Name" help_text="This setting allow the OEM input a name designation for each flash component being used. Note: This is a free form entry field it does not affect actual flash component operation." key="DescriptorPlugin:VsccTable:5/VsccEntryName"/>
<VsccEntryVendorId value="0xC8" label="Vendor ID" help_text="This configures the JEDEC vendor specific byte ID of the SPI flash &amp;lt;br /&amp;gt;Component see Canonlake H / LP SPI Programming guide for further details." key="DescriptorPlugin:VsccTable:5/VsccEntryVendorId"/>
<VsccEntryDeviceId0 value="0x40" label="Device ID 0" help_text="This configures the JEDEC device specific byte ID 0 of the SPI flash Component see Canonlake H / LP SPI Programming guide for further details." key="DescriptorPlugin:VsccTable:5/VsccEntryDeviceId0"/>
<VsccEntryDeviceId1 value="0x18" label="Device ID 1" help_text="This configures the JEDEC device specific byte ID 1 of the SPI flash Component see Canonlake H / LP SPI Programming guide for further details." key="DescriptorPlugin:VsccTable:5/VsccEntryDeviceId1"/>
</VsccEntry>
<VsccEntry label="VSCC Entry">
<VsccEntryActive value="true" value_list="['false', 'true']" label="Active" help_text="" key="DescriptorPlugin:VsccTable:6/VsccEntryActive"/>
<VsccEntryName value="GD25B64C" label="Part Name" help_text="This setting allow the OEM input a name designation for each flash component being used. Note: This is a free form entry field it does not affect actual flash component operation." key="DescriptorPlugin:VsccTable:6/VsccEntryName"/>
<VsccEntryVendorId value="0xC8" label="Vendor ID" help_text="This configures the JEDEC vendor specific byte ID of the SPI flash &amp;lt;br /&amp;gt;Component see Canonlake H / LP SPI Programming guide for further details." key="DescriptorPlugin:VsccTable:6/VsccEntryVendorId"/>
<VsccEntryDeviceId0 value="0x40" label="Device ID 0" help_text="This configures the JEDEC device specific byte ID 0 of the SPI flash Component see Canonlake H / LP SPI Programming guide for further details." key="DescriptorPlugin:VsccTable:6/VsccEntryDeviceId0"/>
<VsccEntryDeviceId1 value="0x17" label="Device ID 1" help_text="This configures the JEDEC device specific byte ID 1 of the SPI flash Component see Canonlake H / LP SPI Programming guide for further details." key="DescriptorPlugin:VsccTable:6/VsccEntryDeviceId1"/>
</VsccEntry>
<VsccEntry label="VSCC Entry">
<VsccEntryActive value="false" value_list="['false', 'true']" label="Active" help_text="" key="DescriptorPlugin:VsccTable:7/VsccEntryActive"/>
<VsccEntryName value="ATF26DF321" label="Part Name" help_text="This setting allow the OEM input a name designation for each flash component being used. Note: This is a free form entry field it does not affect actual flash component operation." key="DescriptorPlugin:VsccTable:7/VsccEntryName"/>
<VsccEntryVendorId value="0x1F" label="Vendor ID" help_text="This configures the JEDEC vendor specific byte ID of the SPI flash &amp;lt;br /&amp;gt;Component see Canonlake H / LP SPI Programming guide for further details." key="DescriptorPlugin:VsccTable:7/VsccEntryVendorId"/>
<VsccEntryDeviceId0 value="0x47" label="Device ID 0" help_text="This configures the JEDEC device specific byte ID 0 of the SPI flash Component see Canonlake H / LP SPI Programming guide for further details." key="DescriptorPlugin:VsccTable:7/VsccEntryDeviceId0"/>
<VsccEntryDeviceId1 value="0x0" label="Device ID 1" help_text="This configures the JEDEC device specific byte ID 1 of the SPI flash Component see Canonlake H / LP SPI Programming guide for further details." key="DescriptorPlugin:VsccTable:7/VsccEntryDeviceId1"/>
</VsccEntry>
<VsccEntry label="VSCC Entry">
<VsccEntryActive value="false" value_list="['false', 'true']" label="Active" help_text="" key="DescriptorPlugin:VsccTable:8/VsccEntryActive"/>
<VsccEntryName value="ATF26DF321" label="Part Name" help_text="This setting allow the OEM input a name designation for each flash component being used. Note: This is a free form entry field it does not affect actual flash component operation." key="DescriptorPlugin:VsccTable:8/VsccEntryName"/>
<VsccEntryVendorId value="0x1F" label="Vendor ID" help_text="This configures the JEDEC vendor specific byte ID of the SPI flash &amp;lt;br /&amp;gt;Component see Canonlake H / LP SPI Programming guide for further details." key="DescriptorPlugin:VsccTable:8/VsccEntryVendorId"/>
<VsccEntryDeviceId0 value="0x47" label="Device ID 0" help_text="This configures the JEDEC device specific byte ID 0 of the SPI flash Component see Canonlake H / LP SPI Programming guide for further details." key="DescriptorPlugin:VsccTable:8/VsccEntryDeviceId0"/>
<VsccEntryDeviceId1 value="0x0" label="Device ID 1" help_text="This configures the JEDEC device specific byte ID 1 of the SPI flash Component see Canonlake H / LP SPI Programming guide for further details." key="DescriptorPlugin:VsccTable:8/VsccEntryDeviceId1"/>
</VsccEntry>
<VsccEntry label="VSCC Entry">
<VsccEntryActive value="false" value_list="['false', 'true']" label="Active" help_text="" key="DescriptorPlugin:VsccTable:9/VsccEntryActive"/>
<VsccEntryName value="ATF26DF321" label="Part Name" help_text="This setting allow the OEM input a name designation for each flash component being used. Note: This is a free form entry field it does not affect actual flash component operation." key="DescriptorPlugin:VsccTable:9/VsccEntryName"/>
<VsccEntryVendorId value="0x1F" label="Vendor ID" help_text="This configures the JEDEC vendor specific byte ID of the SPI flash &amp;lt;br /&amp;gt;Component see Canonlake H / LP SPI Programming guide for further details." key="DescriptorPlugin:VsccTable:9/VsccEntryVendorId"/>
<VsccEntryDeviceId0 value="0x47" label="Device ID 0" help_text="This configures the JEDEC device specific byte ID 0 of the SPI flash Component see Canonlake H / LP SPI Programming guide for further details." key="DescriptorPlugin:VsccTable:9/VsccEntryDeviceId0"/>
<VsccEntryDeviceId1 value="0x0" label="Device ID 1" help_text="This configures the JEDEC device specific byte ID 1 of the SPI flash Component see Canonlake H / LP SPI Programming guide for further details." key="DescriptorPlugin:VsccTable:9/VsccEntryDeviceId1"/>
</VsccEntry>
<VsccEntry label="VSCC Entry">
<VsccEntryActive value="false" value_list="['false', 'true']" label="Active" help_text="" key="DescriptorPlugin:VsccTable:10/VsccEntryActive"/>
<VsccEntryName value="ATF26DF321" label="Part Name" help_text="This setting allow the OEM input a name designation for each flash component being used. Note: This is a free form entry field it does not affect actual flash component operation." key="DescriptorPlugin:VsccTable:10/VsccEntryName"/>
<VsccEntryVendorId value="0x1F" label="Vendor ID" help_text="This configures the JEDEC vendor specific byte ID of the SPI flash &amp;lt;br /&amp;gt;Component see Canonlake H / LP SPI Programming guide for further details." key="DescriptorPlugin:VsccTable:10/VsccEntryVendorId"/>
<VsccEntryDeviceId0 value="0x47" label="Device ID 0" help_text="This configures the JEDEC device specific byte ID 0 of the SPI flash Component see Canonlake H / LP SPI Programming guide for further details." key="DescriptorPlugin:VsccTable:10/VsccEntryDeviceId0"/>
<VsccEntryDeviceId1 value="0x0" label="Device ID 1" help_text="This configures the JEDEC device specific byte ID 1 of the SPI flash Component see Canonlake H / LP SPI Programming guide for further details." key="DescriptorPlugin:VsccTable:10/VsccEntryDeviceId1"/>
</VsccEntry>
<VsccEntry label="VSCC Entry">
<VsccEntryActive value="false" value_list="['false', 'true']" label="Active" help_text="" key="DescriptorPlugin:VsccTable:11/VsccEntryActive"/>
<VsccEntryName value="ATF26DF321" label="Part Name" help_text="This setting allow the OEM input a name designation for each flash component being used. Note: This is a free form entry field it does not affect actual flash component operation." key="DescriptorPlugin:VsccTable:11/VsccEntryName"/>
<VsccEntryVendorId value="0x1F" label="Vendor ID" help_text="This configures the JEDEC vendor specific byte ID of the SPI flash &amp;lt;br /&amp;gt;Component see Canonlake H / LP SPI Programming guide for further details." key="DescriptorPlugin:VsccTable:11/VsccEntryVendorId"/>
<VsccEntryDeviceId0 value="0x47" label="Device ID 0" help_text="This configures the JEDEC device specific byte ID 0 of the SPI flash Component see Canonlake H / LP SPI Programming guide for further details." key="DescriptorPlugin:VsccTable:11/VsccEntryDeviceId0"/>
<VsccEntryDeviceId1 value="0x0" label="Device ID 1" help_text="This configures the JEDEC device specific byte ID 1 of the SPI flash Component see Canonlake H / LP SPI Programming guide for further details." key="DescriptorPlugin:VsccTable:11/VsccEntryDeviceId1"/>
</VsccEntry>
<VsccEntry label="VSCC Entry">
<VsccEntryActive value="false" value_list="['false', 'true']" label="Active" help_text="" key="DescriptorPlugin:VsccTable:12/VsccEntryActive"/>
<VsccEntryName value="ATF26DF321" label="Part Name" help_text="This setting allow the OEM input a name designation for each flash component being used. Note: This is a free form entry field it does not affect actual flash component operation." key="DescriptorPlugin:VsccTable:12/VsccEntryName"/>
<VsccEntryVendorId value="0x1F" label="Vendor ID" help_text="This configures the JEDEC vendor specific byte ID of the SPI flash &amp;lt;br /&amp;gt;Component see Canonlake H / LP SPI Programming guide for further details." key="DescriptorPlugin:VsccTable:12/VsccEntryVendorId"/>
<VsccEntryDeviceId0 value="0x47" label="Device ID 0" help_text="This configures the JEDEC device specific byte ID 0 of the SPI flash Component see Canonlake H / LP SPI Programming guide for further details." key="DescriptorPlugin:VsccTable:12/VsccEntryDeviceId0"/>
<VsccEntryDeviceId1 value="0x0" label="Device ID 1" help_text="This configures the JEDEC device specific byte ID 1 of the SPI flash Component see Canonlake H / LP SPI Programming guide for further details." key="DescriptorPlugin:VsccTable:12/VsccEntryDeviceId1"/>
</VsccEntry>
<VsccEntry label="VSCC Entry">
<VsccEntryActive value="false" value_list="['false', 'true']" label="Active" help_text="" key="DescriptorPlugin:VsccTable:13/VsccEntryActive"/>
<VsccEntryName value="ATF26DF321" label="Part Name" help_text="This setting allow the OEM input a name designation for each flash component being used. Note: This is a free form entry field it does not affect actual flash component operation." key="DescriptorPlugin:VsccTable:13/VsccEntryName"/>
<VsccEntryVendorId value="0x1F" label="Vendor ID" help_text="This configures the JEDEC vendor specific byte ID of the SPI flash &amp;lt;br /&amp;gt;Component see Canonlake H / LP SPI Programming guide for further details." key="DescriptorPlugin:VsccTable:13/VsccEntryVendorId"/>
<VsccEntryDeviceId0 value="0x47" label="Device ID 0" help_text="This configures the JEDEC device specific byte ID 0 of the SPI flash Component see Canonlake H / LP SPI Programming guide for further details." key="DescriptorPlugin:VsccTable:13/VsccEntryDeviceId0"/>
<VsccEntryDeviceId1 value="0x0" label="Device ID 1" help_text="This configures the JEDEC device specific byte ID 1 of the SPI flash Component see Canonlake H / LP SPI Programming guide for further details." key="DescriptorPlugin:VsccTable:13/VsccEntryDeviceId1"/>
</VsccEntry>
<VsccEntry label="VSCC Entry">
<VsccEntryActive value="false" value_list="['false', 'true']" label="Active" help_text="" key="DescriptorPlugin:VsccTable:14/VsccEntryActive"/>
<VsccEntryName value="ATF26DF321" label="Part Name" help_text="This setting allow the OEM input a name designation for each flash component being used. Note: This is a free form entry field it does not affect actual flash component operation." key="DescriptorPlugin:VsccTable:14/VsccEntryName"/>
<VsccEntryVendorId value="0x1F" label="Vendor ID" help_text="This configures the JEDEC vendor specific byte ID of the SPI flash &amp;lt;br /&amp;gt;Component see Canonlake H / LP SPI Programming guide for further details." key="DescriptorPlugin:VsccTable:14/VsccEntryVendorId"/>
<VsccEntryDeviceId0 value="0x47" label="Device ID 0" help_text="This configures the JEDEC device specific byte ID 0 of the SPI flash Component see Canonlake H / LP SPI Programming guide for further details." key="DescriptorPlugin:VsccTable:14/VsccEntryDeviceId0"/>
<VsccEntryDeviceId1 value="0x0" label="Device ID 1" help_text="This configures the JEDEC device specific byte ID 1 of the SPI flash Component see Canonlake H / LP SPI Programming guide for further details." key="DescriptorPlugin:VsccTable:14/VsccEntryDeviceId1"/>
</VsccEntry>
<VsccEntry label="VSCC Entry">
<VsccEntryActive value="false" value_list="['false', 'true']" label="Active" help_text="" key="DescriptorPlugin:VsccTable:15/VsccEntryActive"/>
<VsccEntryName value="ATF26DF321" label="Part Name" help_text="This setting allow the OEM input a name designation for each flash component being used. Note: This is a free form entry field it does not affect actual flash component operation." key="DescriptorPlugin:VsccTable:15/VsccEntryName"/>
<VsccEntryVendorId value="0x1F" label="Vendor ID" help_text="This configures the JEDEC vendor specific byte ID of the SPI flash &amp;lt;br /&amp;gt;Component see Canonlake H / LP SPI Programming guide for further details." key="DescriptorPlugin:VsccTable:15/VsccEntryVendorId"/>
<VsccEntryDeviceId0 value="0x47" label="Device ID 0" help_text="This configures the JEDEC device specific byte ID 0 of the SPI flash Component see Canonlake H / LP SPI Programming guide for further details." key="DescriptorPlugin:VsccTable:15/VsccEntryDeviceId0"/>
<VsccEntryDeviceId1 value="0x0" label="Device ID 1" help_text="This configures the JEDEC device specific byte ID 1 of the SPI flash Component see Canonlake H / LP SPI Programming guide for further details." key="DescriptorPlugin:VsccTable:15/VsccEntryDeviceId1"/>
</VsccEntry>
<VsccEntry label="VSCC Entry">
<VsccEntryActive value="false" value_list="['false', 'true']" label="Active" help_text="" key="DescriptorPlugin:VsccTable:16/VsccEntryActive"/>
<VsccEntryName value="ATF26DF321" label="Part Name" help_text="This setting allow the OEM input a name designation for each flash component being used. Note: This is a free form entry field it does not affect actual flash component operation." key="DescriptorPlugin:VsccTable:16/VsccEntryName"/>
<VsccEntryVendorId value="0x1F" label="Vendor ID" help_text="This configures the JEDEC vendor specific byte ID of the SPI flash &amp;lt;br /&amp;gt;Component see Canonlake H / LP SPI Programming guide for further details." key="DescriptorPlugin:VsccTable:16/VsccEntryVendorId"/>
<VsccEntryDeviceId0 value="0x47" label="Device ID 0" help_text="This configures the JEDEC device specific byte ID 0 of the SPI flash Component see Canonlake H / LP SPI Programming guide for further details." key="DescriptorPlugin:VsccTable:16/VsccEntryDeviceId0"/>
<VsccEntryDeviceId1 value="0x0" label="Device ID 1" help_text="This configures the JEDEC device specific byte ID 1 of the SPI flash Component see Canonlake H / LP SPI Programming guide for further details." key="DescriptorPlugin:VsccTable:16/VsccEntryDeviceId1"/>
</VsccEntry>
<VsccEntry label="VSCC Entry">
<VsccEntryActive value="false" value_list="['false', 'true']" label="Active" help_text="" key="DescriptorPlugin:VsccTable:17/VsccEntryActive"/>
<VsccEntryName value="ATF26DF321" label="Part Name" help_text="This setting allow the OEM input a name designation for each flash component being used. Note: This is a free form entry field it does not affect actual flash component operation." key="DescriptorPlugin:VsccTable:17/VsccEntryName"/>
<VsccEntryVendorId value="0x1F" label="Vendor ID" help_text="This configures the JEDEC vendor specific byte ID of the SPI flash &amp;lt;br /&amp;gt;Component see Canonlake H / LP SPI Programming guide for further details." key="DescriptorPlugin:VsccTable:17/VsccEntryVendorId"/>
<VsccEntryDeviceId0 value="0x47" label="Device ID 0" help_text="This configures the JEDEC device specific byte ID 0 of the SPI flash Component see Canonlake H / LP SPI Programming guide for further details." key="DescriptorPlugin:VsccTable:17/VsccEntryDeviceId0"/>
<VsccEntryDeviceId1 value="0x0" label="Device ID 1" help_text="This configures the JEDEC device specific byte ID 1 of the SPI flash Component see Canonlake H / LP SPI Programming guide for further details." key="DescriptorPlugin:VsccTable:17/VsccEntryDeviceId1"/>
</VsccEntry>
<VsccEntry label="VSCC Entry">
<VsccEntryActive value="false" value_list="['false', 'true']" label="Active" help_text="" key="DescriptorPlugin:VsccTable:18/VsccEntryActive"/>
<VsccEntryName value="ATF26DF321" label="Part Name" help_text="This setting allow the OEM input a name designation for each flash component being used. Note: This is a free form entry field it does not affect actual flash component operation." key="DescriptorPlugin:VsccTable:18/VsccEntryName"/>
<VsccEntryVendorId value="0x1F" label="Vendor ID" help_text="This configures the JEDEC vendor specific byte ID of the SPI flash &amp;lt;br /&amp;gt;Component see Canonlake H / LP SPI Programming guide for further details." key="DescriptorPlugin:VsccTable:18/VsccEntryVendorId"/>
<VsccEntryDeviceId0 value="0x47" label="Device ID 0" help_text="This configures the JEDEC device specific byte ID 0 of the SPI flash Component see Canonlake H / LP SPI Programming guide for further details." key="DescriptorPlugin:VsccTable:18/VsccEntryDeviceId0"/>
<VsccEntryDeviceId1 value="0x0" label="Device ID 1" help_text="This configures the JEDEC device specific byte ID 1 of the SPI flash Component see Canonlake H / LP SPI Programming guide for further details." key="DescriptorPlugin:VsccTable:18/VsccEntryDeviceId1"/>
</VsccEntry>
<VsccEntry label="VSCC Entry">
<VsccEntryActive value="false" value_list="['false', 'true']" label="Active" help_text="" key="DescriptorPlugin:VsccTable:19/VsccEntryActive"/>
<VsccEntryName value="ATF26DF321" label="Part Name" help_text="This setting allow the OEM input a name designation for each flash component being used. Note: This is a free form entry field it does not affect actual flash component operation." key="DescriptorPlugin:VsccTable:19/VsccEntryName"/>
<VsccEntryVendorId value="0x1F" label="Vendor ID" help_text="This configures the JEDEC vendor specific byte ID of the SPI flash &amp;lt;br /&amp;gt;Component see Canonlake H / LP SPI Programming guide for further details." key="DescriptorPlugin:VsccTable:19/VsccEntryVendorId"/>
<VsccEntryDeviceId0 value="0x47" label="Device ID 0" help_text="This configures the JEDEC device specific byte ID 0 of the SPI flash Component see Canonlake H / LP SPI Programming guide for further details." key="DescriptorPlugin:VsccTable:19/VsccEntryDeviceId0"/>
<VsccEntryDeviceId1 value="0x0" label="Device ID 1" help_text="This configures the JEDEC device specific byte ID 1 of the SPI flash Component see Canonlake H / LP SPI Programming guide for further details." key="DescriptorPlugin:VsccTable:19/VsccEntryDeviceId1"/>
</VsccEntry>
<VsccEntry label="VSCC Entry">
<VsccEntryActive value="false" value_list="['false', 'true']" label="Active" help_text="" key="DescriptorPlugin:VsccTable:20/VsccEntryActive"/>
<VsccEntryName value="ATF26DF321" label="Part Name" help_text="This setting allow the OEM input a name designation for each flash component being used. Note: This is a free form entry field it does not affect actual flash component operation." key="DescriptorPlugin:VsccTable:20/VsccEntryName"/>
<VsccEntryVendorId value="0x1F" label="Vendor ID" help_text="This configures the JEDEC vendor specific byte ID of the SPI flash &amp;lt;br /&amp;gt;Component see Canonlake H / LP SPI Programming guide for further details." key="DescriptorPlugin:VsccTable:20/VsccEntryVendorId"/>
<VsccEntryDeviceId0 value="0x47" label="Device ID 0" help_text="This configures the JEDEC device specific byte ID 0 of the SPI flash Component see Canonlake H / LP SPI Programming guide for further details." key="DescriptorPlugin:VsccTable:20/VsccEntryDeviceId0"/>
<VsccEntryDeviceId1 value="0x0" label="Device ID 1" help_text="This configures the JEDEC device specific byte ID 1 of the SPI flash Component see Canonlake H / LP SPI Programming guide for further details." key="DescriptorPlugin:VsccTable:20/VsccEntryDeviceId1"/>
</VsccEntry>
<VsccEntry label="VSCC Entry">
<VsccEntryActive value="false" value_list="['false', 'true']" label="Active" help_text="" key="DescriptorPlugin:VsccTable:21/VsccEntryActive"/>
<VsccEntryName value="ATF26DF321" label="Part Name" help_text="This setting allow the OEM input a name designation for each flash component being used. Note: This is a free form entry field it does not affect actual flash component operation." key="DescriptorPlugin:VsccTable:21/VsccEntryName"/>
<VsccEntryVendorId value="0x1F" label="Vendor ID" help_text="This configures the JEDEC vendor specific byte ID of the SPI flash &amp;lt;br /&amp;gt;Component see Canonlake H / LP SPI Programming guide for further details." key="DescriptorPlugin:VsccTable:21/VsccEntryVendorId"/>
<VsccEntryDeviceId0 value="0x47" label="Device ID 0" help_text="This configures the JEDEC device specific byte ID 0 of the SPI flash Component see Canonlake H / LP SPI Programming guide for further details." key="DescriptorPlugin:VsccTable:21/VsccEntryDeviceId0"/>
<VsccEntryDeviceId1 value="0x0" label="Device ID 1" help_text="This configures the JEDEC device specific byte ID 1 of the SPI flash Component see Canonlake H / LP SPI Programming guide for further details." key="DescriptorPlugin:VsccTable:21/VsccEntryDeviceId1"/>
</VsccEntry>
<VsccEntry label="VSCC Entry">
<VsccEntryActive value="false" value_list="['false', 'true']" label="Active" help_text="" key="DescriptorPlugin:VsccTable:22/VsccEntryActive"/>
<VsccEntryName value="ATF26DF321" label="Part Name" help_text="This setting allow the OEM input a name designation for each flash component being used. Note: This is a free form entry field it does not affect actual flash component operation." key="DescriptorPlugin:VsccTable:22/VsccEntryName"/>
<VsccEntryVendorId value="0x1F" label="Vendor ID" help_text="This configures the JEDEC vendor specific byte ID of the SPI flash &amp;lt;br /&amp;gt;Component see Canonlake H / LP SPI Programming guide for further details." key="DescriptorPlugin:VsccTable:22/VsccEntryVendorId"/>
<VsccEntryDeviceId0 value="0x47" label="Device ID 0" help_text="This configures the JEDEC device specific byte ID 0 of the SPI flash Component see Canonlake H / LP SPI Programming guide for further details." key="DescriptorPlugin:VsccTable:22/VsccEntryDeviceId0"/>
<VsccEntryDeviceId1 value="0x0" label="Device ID 1" help_text="This configures the JEDEC device specific byte ID 1 of the SPI flash Component see Canonlake H / LP SPI Programming guide for further details." key="DescriptorPlugin:VsccTable:22/VsccEntryDeviceId1"/>
</VsccEntry>
<VsccEntry label="VSCC Entry">
<VsccEntryActive value="false" value_list="['false', 'true']" label="Active" help_text="" key="DescriptorPlugin:VsccTable:23/VsccEntryActive"/>
<VsccEntryName value="ATF26DF321" label="Part Name" help_text="This setting allow the OEM input a name designation for each flash component being used. Note: This is a free form entry field it does not affect actual flash component operation." key="DescriptorPlugin:VsccTable:23/VsccEntryName"/>
<VsccEntryVendorId value="0x1F" label="Vendor ID" help_text="This configures the JEDEC vendor specific byte ID of the SPI flash &amp;lt;br /&amp;gt;Component see Canonlake H / LP SPI Programming guide for further details." key="DescriptorPlugin:VsccTable:23/VsccEntryVendorId"/>
<VsccEntryDeviceId0 value="0x47" label="Device ID 0" help_text="This configures the JEDEC device specific byte ID 0 of the SPI flash Component see Canonlake H / LP SPI Programming guide for further details." key="DescriptorPlugin:VsccTable:23/VsccEntryDeviceId0"/>
<VsccEntryDeviceId1 value="0x0" label="Device ID 1" help_text="This configures the JEDEC device specific byte ID 1 of the SPI flash Component see Canonlake H / LP SPI Programming guide for further details." key="DescriptorPlugin:VsccTable:23/VsccEntryDeviceId1"/>
</VsccEntry>
<VsccEntry label="VSCC Entry">
<VsccEntryActive value="false" value_list="['false', 'true']" label="Active" help_text="" key="DescriptorPlugin:VsccTable:24/VsccEntryActive"/>
<VsccEntryName value="ATF26DF321" label="Part Name" help_text="This setting allow the OEM input a name designation for each flash component being used. Note: This is a free form entry field it does not affect actual flash component operation." key="DescriptorPlugin:VsccTable:24/VsccEntryName"/>
<VsccEntryVendorId value="0x1F" label="Vendor ID" help_text="This configures the JEDEC vendor specific byte ID of the SPI flash &amp;lt;br /&amp;gt;Component see Canonlake H / LP SPI Programming guide for further details." key="DescriptorPlugin:VsccTable:24/VsccEntryVendorId"/>
<VsccEntryDeviceId0 value="0x47" label="Device ID 0" help_text="This configures the JEDEC device specific byte ID 0 of the SPI flash Component see Canonlake H / LP SPI Programming guide for further details." key="DescriptorPlugin:VsccTable:24/VsccEntryDeviceId0"/>
<VsccEntryDeviceId1 value="0x0" label="Device ID 1" help_text="This configures the JEDEC device specific byte ID 1 of the SPI flash Component see Canonlake H / LP SPI Programming guide for further details." key="DescriptorPlugin:VsccTable:24/VsccEntryDeviceId1"/>
</VsccEntry>
<VsccEntry label="VSCC Entry">
<VsccEntryActive value="false" value_list="['false', 'true']" label="Active" help_text="" key="DescriptorPlugin:VsccTable:25/VsccEntryActive"/>
<VsccEntryName value="ATF26DF321" label="Part Name" help_text="This setting allow the OEM input a name designation for each flash component being used. Note: This is a free form entry field it does not affect actual flash component operation." key="DescriptorPlugin:VsccTable:25/VsccEntryName"/>
<VsccEntryVendorId value="0x1F" label="Vendor ID" help_text="This configures the JEDEC vendor specific byte ID of the SPI flash &amp;lt;br /&amp;gt;Component see Canonlake H / LP SPI Programming guide for further details." key="DescriptorPlugin:VsccTable:25/VsccEntryVendorId"/>
<VsccEntryDeviceId0 value="0x47" label="Device ID 0" help_text="This configures the JEDEC device specific byte ID 0 of the SPI flash Component see Canonlake H / LP SPI Programming guide for further details." key="DescriptorPlugin:VsccTable:25/VsccEntryDeviceId0"/>
<VsccEntryDeviceId1 value="0x0" label="Device ID 1" help_text="This configures the JEDEC device specific byte ID 1 of the SPI flash Component see Canonlake H / LP SPI Programming guide for further details." key="DescriptorPlugin:VsccTable:25/VsccEntryDeviceId1"/>
</VsccEntry>
<VsccEntry label="VSCC Entry">
<VsccEntryActive value="false" value_list="['false', 'true']" label="Active" help_text="" key="DescriptorPlugin:VsccTable:26/VsccEntryActive"/>
<VsccEntryName value="ATF26DF321" label="Part Name" help_text="This setting allow the OEM input a name designation for each flash component being used. Note: This is a free form entry field it does not affect actual flash component operation." key="DescriptorPlugin:VsccTable:26/VsccEntryName"/>
<VsccEntryVendorId value="0x1F" label="Vendor ID" help_text="This configures the JEDEC vendor specific byte ID of the SPI flash &amp;lt;br /&amp;gt;Component see Canonlake H / LP SPI Programming guide for further details." key="DescriptorPlugin:VsccTable:26/VsccEntryVendorId"/>
<VsccEntryDeviceId0 value="0x47" label="Device ID 0" help_text="This configures the JEDEC device specific byte ID 0 of the SPI flash Component see Canonlake H / LP SPI Programming guide for further details." key="DescriptorPlugin:VsccTable:26/VsccEntryDeviceId0"/>
<VsccEntryDeviceId1 value="0x0" label="Device ID 1" help_text="This configures the JEDEC device specific byte ID 1 of the SPI flash Component see Canonlake H / LP SPI Programming guide for further details." key="DescriptorPlugin:VsccTable:26/VsccEntryDeviceId1"/>
</VsccEntry>
<VsccEntry label="VSCC Entry">
<VsccEntryActive value="false" value_list="['false', 'true']" label="Active" help_text="" key="DescriptorPlugin:VsccTable:27/VsccEntryActive"/>
<VsccEntryName value="ATF26DF321" label="Part Name" help_text="This setting allow the OEM input a name designation for each flash component being used. Note: This is a free form entry field it does not affect actual flash component operation." key="DescriptorPlugin:VsccTable:27/VsccEntryName"/>
<VsccEntryVendorId value="0x1F" label="Vendor ID" help_text="This configures the JEDEC vendor specific byte ID of the SPI flash &amp;lt;br /&amp;gt;Component see Canonlake H / LP SPI Programming guide for further details." key="DescriptorPlugin:VsccTable:27/VsccEntryVendorId"/>
<VsccEntryDeviceId0 value="0x47" label="Device ID 0" help_text="This configures the JEDEC device specific byte ID 0 of the SPI flash Component see Canonlake H / LP SPI Programming guide for further details." key="DescriptorPlugin:VsccTable:27/VsccEntryDeviceId0"/>
<VsccEntryDeviceId1 value="0x0" label="Device ID 1" help_text="This configures the JEDEC device specific byte ID 1 of the SPI flash Component see Canonlake H / LP SPI Programming guide for further details." key="DescriptorPlugin:VsccTable:27/VsccEntryDeviceId1"/>
</VsccEntry>
<VsccEntry label="VSCC Entry">
<VsccEntryActive value="false" value_list="['false', 'true']" label="Active" help_text="" key="DescriptorPlugin:VsccTable:28/VsccEntryActive"/>
<VsccEntryName value="ATF26DF321" label="Part Name" help_text="This setting allow the OEM input a name designation for each flash component being used. Note: This is a free form entry field it does not affect actual flash component operation." key="DescriptorPlugin:VsccTable:28/VsccEntryName"/>
<VsccEntryVendorId value="0x1F" label="Vendor ID" help_text="This configures the JEDEC vendor specific byte ID of the SPI flash &amp;lt;br /&amp;gt;Component see Canonlake H / LP SPI Programming guide for further details." key="DescriptorPlugin:VsccTable:28/VsccEntryVendorId"/>
<VsccEntryDeviceId0 value="0x47" label="Device ID 0" help_text="This configures the JEDEC device specific byte ID 0 of the SPI flash Component see Canonlake H / LP SPI Programming guide for further details." key="DescriptorPlugin:VsccTable:28/VsccEntryDeviceId0"/>
<VsccEntryDeviceId1 value="0x0" label="Device ID 1" help_text="This configures the JEDEC device specific byte ID 1 of the SPI flash Component see Canonlake H / LP SPI Programming guide for further details." key="DescriptorPlugin:VsccTable:28/VsccEntryDeviceId1"/>
</VsccEntry>
<VsccEntry label="VSCC Entry">
<VsccEntryActive value="false" value_list="['false', 'true']" label="Active" help_text="" key="DescriptorPlugin:VsccTable:29/VsccEntryActive"/>
<VsccEntryName value="ATF26DF321" label="Part Name" help_text="This setting allow the OEM input a name designation for each flash component being used. Note: This is a free form entry field it does not affect actual flash component operation." key="DescriptorPlugin:VsccTable:29/VsccEntryName"/>
<VsccEntryVendorId value="0x1F" label="Vendor ID" help_text="This configures the JEDEC vendor specific byte ID of the SPI flash &amp;lt;br /&amp;gt;Component see Canonlake H / LP SPI Programming guide for further details." key="DescriptorPlugin:VsccTable:29/VsccEntryVendorId"/>
<VsccEntryDeviceId0 value="0x47" label="Device ID 0" help_text="This configures the JEDEC device specific byte ID 0 of the SPI flash Component see Canonlake H / LP SPI Programming guide for further details." key="DescriptorPlugin:VsccTable:29/VsccEntryDeviceId0"/>
<VsccEntryDeviceId1 value="0x0" label="Device ID 1" help_text="This configures the JEDEC device specific byte ID 1 of the SPI flash Component see Canonlake H / LP SPI Programming guide for further details." key="DescriptorPlugin:VsccTable:29/VsccEntryDeviceId1"/>
</VsccEntry>
<VsccEntry label="VSCC Entry">
<VsccEntryActive value="false" value_list="['false', 'true']" label="Active" help_text="" key="DescriptorPlugin:VsccTable:30/VsccEntryActive"/>
<VsccEntryName value="ATF26DF321" label="Part Name" help_text="This setting allow the OEM input a name designation for each flash component being used. Note: This is a free form entry field it does not affect actual flash component operation." key="DescriptorPlugin:VsccTable:30/VsccEntryName"/>
<VsccEntryVendorId value="0x1F" label="Vendor ID" help_text="This configures the JEDEC vendor specific byte ID of the SPI flash &amp;lt;br /&amp;gt;Component see Canonlake H / LP SPI Programming guide for further details." key="DescriptorPlugin:VsccTable:30/VsccEntryVendorId"/>
<VsccEntryDeviceId0 value="0x47" label="Device ID 0" help_text="This configures the JEDEC device specific byte ID 0 of the SPI flash Component see Canonlake H / LP SPI Programming guide for further details." key="DescriptorPlugin:VsccTable:30/VsccEntryDeviceId0"/>
<VsccEntryDeviceId1 value="0x0" label="Device ID 1" help_text="This configures the JEDEC device specific byte ID 1 of the SPI flash Component see Canonlake H / LP SPI Programming guide for further details." key="DescriptorPlugin:VsccTable:30/VsccEntryDeviceId1"/>
</VsccEntry>
<VsccEntry label="VSCC Entry">
<VsccEntryActive value="false" value_list="['false', 'true']" label="Active" help_text="" key="DescriptorPlugin:VsccTable:31/VsccEntryActive"/>
<VsccEntryName value="ATF26DF321" label="Part Name" help_text="This setting allow the OEM input a name designation for each flash component being used. Note: This is a free form entry field it does not affect actual flash component operation." key="DescriptorPlugin:VsccTable:31/VsccEntryName"/>
<VsccEntryVendorId value="0x1F" label="Vendor ID" help_text="This configures the JEDEC vendor specific byte ID of the SPI flash &amp;lt;br /&amp;gt;Component see Canonlake H / LP SPI Programming guide for further details." key="DescriptorPlugin:VsccTable:31/VsccEntryVendorId"/>
<VsccEntryDeviceId0 value="0x47" label="Device ID 0" help_text="This configures the JEDEC device specific byte ID 0 of the SPI flash Component see Canonlake H / LP SPI Programming guide for further details." key="DescriptorPlugin:VsccTable:31/VsccEntryDeviceId0"/>
<VsccEntryDeviceId1 value="0x0" label="Device ID 1" help_text="This configures the JEDEC device specific byte ID 1 of the SPI flash Component see Canonlake H / LP SPI Programming guide for further details." key="DescriptorPlugin:VsccTable:31/VsccEntryDeviceId1"/>
</VsccEntry>
</VsccEntries>
</VsccTable>
<BiosConfiguration label="BIOS Configuration">
<TopSwapOverride value="4MB" value_list="['64KB', '128KB', '256KB', '512KB', '1MB', '2MB', '4MB', '8MB']" label="Top Swap Block Size" help_text="This configures the Top Swap Block size for the platform. For further details see Alder Lake Platform Controller Hub EDS." key="DescriptorPlugin:PchStraps:PCH_Strap_SPI_BOOT_BLOCK_SIZE"/>
<BiosRedAssistance value="Disabled" value_list="['Disabled', 'Enabled']" label="BIOS Redundancy Assistance" help_text="In case of BIOS boot failure, CSME will configure the platform to boot with backup BIOS using Top Swap. Note: This option is only available when Boot Guard is enabled." key="CsePlugin:AutoNvars:BrmEn#BiosRedAssistance"/>
</BiosConfiguration>
<FPFConfiguration label="FPF Configuration">
<HwBindingEn value="Disabled" value_list="['Disabled', 'Enabled']" label="Hardware Binding Enabled" help_text="This setting configures the FPF Hardware and RPMC / RPMB binding behavior for the platform image.
If this setting is enabled FPF Hardware and RPMC / RPMB binding behavior will occur when platform close manufacturing flow is executed with Intel(R) FPT.
If this setting is disabled FPF Hardware and RPMC / RPMB binding behavior will not take place when close manufacturing flow is executed.
Note: For Revenue parts this setting will be ignored and FPF Hardware and RPMC / RPMB binding behavior will take place when close manufacturing flow is executed." key="CsePlugin:AutoNvars:HwBinding#HwBindingEn"/>
</FPFConfiguration>
<RpmcConfiguration label="RPMC Configuration">
<RpmcSupported value="Yes" value_list="['No', 'Yes']" label="RPMC Supported" help_text="This setting determines if RPMC is enabled. Note: The SPI parts being used need to support RPMC In order to use this feature." key="CsePlugin:UEP:RpmcSupported"/>
<RpmcRebindEn value="Yes" value_list="['No', 'Yes']" label="RPMC Rebinding Enabled" help_text="This setting determines if Rebinding of RPMC enabled SPI parts is enabled." key="CsePlugin:UEP:RpmcRebindEn"/>
</RpmcConfiguration>
</FlashSettings>
<IntelMeKernel label="Intel Me Kernel">
<Processor label="Processor">
<ProcEmulation value="No Emulation" value_list="['No Emulation', 'EMULATE Intel (R) vPro (TM) capable Processor', 'EMULATE Intel (R) Core (TM) branded Processor', 'EMULATE Intel (R) Celeron (R) branded Processor', 'EMULATE Intel (R) Pentium (R) branded Processor', 'EMULATE Intel (R) Xeon E (R) branded Processor', 'EMULATE Intel (R) Xeon W (R) Manageability capable Processor']" label="Processor Emulation" help_text="This setting determines processor type to be emulated on pre-production silicon." key="CsePlugin:AutoNvars:ME_CONF_WRK#ProcEmulation"/>
</Processor>
<IntelMeFirmwareUpdate label="Intel(R) ME Firmware Update">
<HideMEBxFwUpdCtrl value="No" value_list="['No', 'Yes']" label="Hide MEBx Firmware Update Control" help_text="This setting allows customers to hide the Firmware Update option in the MEBx interface." key="CsePlugin:AutoNvars:ME_CONF_WRK#HideMEBxFwUpdCtrl"/>
<FwUpdateOemId value="00000000-0000-0000-0000-000000000000" label="Firmware Update OEM ID" help_text="This setting allows configuration of an OEM unique ID to ensure that customers can only update their platform with images from the OEM of the platform." key="CsePlugin:AutoNvars:OEM_ID_STRING#FwUpdateOemId"/>
<HmrfpoEnable value="Yes" value_list="['No', 'Yes']" label="Intel(R) ME Region Flash Protection Override" help_text="This setting enables descriptor unlock of the ME Region when the HMRFPO message is sent to firmware prior to BIOS End of POST." key="CsePlugin:AutoNvars:HMRFPO_OEM_Enabled#HmrfpoEnable"/>
<OemFwVersion value="0x0" label="OEM FW Version" help_text="This setting contains the OEM IP version" key="CsePlugin:AutoNvars:EOM_VERSION#OemFwVersion"/>
</IntelMeFirmwareUpdate>
<ImageIdentification label="Image Identification">
<OemTag value="0x0" label="OEM Tag" help_text="This is a free form 32bit field that allows the OEM to configure their own unique identifier in the firmware image." key="CsePlugin:AutoNvars:ME_CONF_WRK#OemTag"/>
</ImageIdentification>
<FirmwareDiagnostics label="Firmware Diagnostics">
<FwAutoBist value="Disabled" value_list="['Disabled', 'Enabled']" label="Automatic Built in Self Test" help_text="This setting enables the firmware Automatic Built in Self Test which is executed during first platform boot after initial image flashing." key="CsePlugin:AutoNvars:BistMeAutoBistConfAndStatus#FwAutoBist"/>
</FirmwareDiagnostics>
<EndofManufacturingConfiguration label="End of Manufacturing Configuration">
<FlexibleEomSettings value="Lock Descriptor and OEM Configs" value_list="['Lock Descriptor and OEM Configs', 'Lock OEM Configs Only', 'Lock Descriptor Only', 'Do not lock Descriptor and OEM Configs']" label="Flexible EOM setting options" help_text="This setting deteremines which settings will be automatically commited during End of Manufacturing flows.
Note: The FPFs, RPMB / RPMC and set manufacturing mode settings are mandatory and cannot be overridden revenue parts. Simulation can be done on non-revenue part with the Hardware binding set to disabled." key="CsePlugin:EomNvar:EOM_Config#FlexibleEomSettings"/>
<EomFirstBootEnabled value="No" value_list="['No', 'Yes']" label="EOM on First Boot Enabled" help_text="This setting determines if End of Manufacturing will be triggered on first boot of the platform after flashing.
Note: When this setting is enabled Intel(R) CSME will enter End of Manufacturing regardless of the descriptor settings." key="CsePlugin:EomNvar:EOM#EomFirstBootEnabled"/>
</EndofManufacturingConfiguration>
<MctpConfiguration label="MCTP Configuration">
<MctpDevicePortEc value="0x2" label="MctpDevicePortEc" help_text="" key="CsePlugin:AutoNvars:MctpDevicePorts#MctpDevicePortEc"/>
<MctpDevicePortSio value="0x0" label="MctpDevicePortSio" help_text="" key="CsePlugin:AutoNvars:MctpDevicePorts#MctpDevicePortSio"/>
<MctpDevicePortIsh value="0x0" label="MctpDevicePortIsh" help_text="" key="CsePlugin:AutoNvars:MctpDevicePorts#MctpDevicePortIsh"/>
<MctpDevicePortBmc value="0x0" label="MctpDevicePortBmc" help_text="" key="CsePlugin:AutoNvars:MctpDevicePorts#MctpDevicePortBmc"/>
</MctpConfiguration>
<IntelMeBootConfiguration label="Intel(R) ME Boot Configuration">
<PrtcBackupPower value="Exists" value_list="['Exists', 'None']" label="Persistent PRTC Backup Power" help_text="FPF that indicates if the device is designed such that it may lose PRTC power more than 10 times throughout the normal lifecycle of the product and hence has no persistent time or AR protection. At EOM, this value is burned to an FPF, and can never be changed." key="CsePlugin:UEP:PrtcBackupPower"/>
</IntelMeBootConfiguration>
<IntelMeMeasuredBootConfiguration label="Intel (R) Me Measured Boot Configuration">
<MeMeasuredBootState value="Disabled" value_list="['Disabled', 'Enabled']" label="Intel(R) ME Measured Boot State" help_text="When measured boot is enabled firmware will use additional extended registers for all IUPs and Key Manifests that firmware loads and verifies from flash.
Note: When measured boot is enabled any IUPs or firmware updates will require a global reset" key="CsePlugin:AutoNvars:MeasurmentSupport#MeMeasuredBootState"/>
</IntelMeMeasuredBootConfiguration>
<IntelMeAssistedBootConfiguration label="Intel(R) ME Assisted Boot Configuration">
<MeBiosBootAssist value="Normal" value_list="['Normal', 'Intel(R) ME Assisted']" label="Intel(R) ME Assisted BIOS Boot" help_text="This setting configures Intel(R) ME Assisted BIOS Boot capabilities." key="DescriptorPlugin:PchStraps:PCH_Strap_DMI_CABB"/>
</IntelMeAssistedBootConfiguration>
<Reserved label="Reserved">
<Reserved value="No" value_list="['No', 'Yes']" label="Reserved" help_text="" key="DescriptorPlugin:PchStraps:PCH_Strap_CSME_CSE_HAP_Mode"/>
</Reserved>
</IntelMeKernel>
<PlatformProtection label="Platform Protection">
<ContentProtection label="Content Protection">
<PavpSupported value="Yes" value_list="['No', 'Yes']" label="PAVP Supported" help_text="This setting determines if the Protected Audio Video Path (PAVP) feature will be permanently disabled in the FW image." key="CsePlugin:ConfigRulesNvar:ME_CONF_WRK#PavpSupported"/>
<Hdcp5kedisp1 value="PortA" value_list="['None', 'PortA', 'PortB', 'PortC']" label="HDCP Internal Display Port 1 - 5K" help_text="This setting determines which port is connected to internal display 1" key="CsePlugin:PavpHdcpNvar:PavpHdcp#Hdcp5kedisp1"/>
<Hdcp5kedisp2 value="None" value_list="['None', 'PortA', 'PortB', 'PortC']" label="HDCP Internal Display Port 2 - 5K" help_text="This setting determines which port is connected to internal display 2" key="CsePlugin:PavpHdcpNvar:PavpHdcp#Hdcp5kedisp2"/>
</ContentProtection>
<PlatformIntegrity label="Hash Key Configuration for Bootguard / ISH">
<SkipOemKeysCheck value="No" value_list="['No', 'Yes']" label="Skip OEM Keys Check" help_text="This is meant for debugging purposes only. Enabling this parameter impacts image creation procedure in FIT tool only." key="CsePlugin:CseRegion:SkipOemKeysCheck"/>
<OemExtInputFile value="" label="OEM Key Manifest Binary" help_text="Signed manifest file containing hashes of keys used for signing components of image. This setting is only configurable when OEM signing is enabled (See Hash Key Configuration for Bootguard/ISH/OemPublicKeyHash)." key="CsePlugin:OEM_KM:OemExtInputFile_path"/>
<OemKeyRevEnable value="No" value_list="['No', 'Yes']" label="Oem Key Revocation Enable" help_text="Enabling the OEM key revocation mechanism requires 'OEM Public Key Hash' and 'Second OEM key hash' to be configured." key="CsePlugin:UEP:OemKeyRevEnable"/>
<OemPublicKeyHash value="00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00" label="OEM Public Key Hash" help_text="Raw hash string for the SHA-384 hash of the OEM public key corresponding to the private key used to sign the OEM Key hash manifest. When manufacture is completed, this hash value is burned into an FPF, and is permament. This value is used to verify the OEM Key hash, and also DnX images. OEM signing is disabled when this hash is set to all 0s." key="CsePlugin:UEP:OemPublicKeyHash"/>
<SecondOemPublicKeyHash value="00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00" label="Second OEM key hash" help_text="" key="CsePlugin:UEP:SecondOemPublicKeyHash"/>
</PlatformIntegrity>
<DescConfiguration label="Descriptor Configuration">
<excludeMasterAccsess value="Yes" value_list="['No', 'Yes']" label="Exclude master access in the signature" help_text="include/exclude master access in the signature." key="DescriptorPlugin:HashDescriptorManifestExt:exclude_master_accsess"/>
<FdvEnabled value="No" value_list="['No', 'Yes']" label="Flash Descriptor Verification Enabled" help_text="" key="CsePlugin:UEP:FdvEnabled"/>
</DescConfiguration>
<ExclusionRanges label="Exclusion Ranges">
<Range1Offset value="0x800" label="Range 1 offset" help_text="Range 1 offset covers manifest, cannot be changed" key="DescriptorPlugin:HashDescriptorManifestExt:range_1_offset"/>
<Range1Size value="0x400" label="Range 1 size" help_text="Range 1 size covers manifest, cannot be changed" key="DescriptorPlugin:HashDescriptorManifestExt:range_1_size"/>
<Range2Offset value="0x80" label="Range 2 offset" help_text="Range 2 offset covers master accsess ofsset" key="DescriptorPlugin:HashDescriptorManifestExt:range_2_offset"/>
<Range2Size value="0x20" label="Range 2 size" help_text="Range 2 size covers master accsess size" key="DescriptorPlugin:HashDescriptorManifestExt:range_2_size"/>
<Range3Offset value="0x0" label="Range 3 offset" help_text="Range 3 offset covers OEM defined unprotected range start" key="DescriptorPlugin:HashDescriptorManifestExt:range_3_offset"/>
<Range3Size value="0x0" label="Range 3 size" help_text="Range 3 size covers OEM defined unprotected range length" key="DescriptorPlugin:HashDescriptorManifestExt:range_3_size"/>
<Range4Offset value="0x0" label="Range 4 offset" help_text="Range 4 offset covers OEM defined unprotected range start" key="DescriptorPlugin:HashDescriptorManifestExt:range_4_offset"/>
<Range4Size value="0x0" label="Range 4 size" help_text="Range 4 size covers OEM defined unprotected range length" key="DescriptorPlugin:HashDescriptorManifestExt:range_4_size"/>
<Range5Offset value="0x0" label="Range 5 offset" help_text="Range 5 offset covers OEM defined unprotected range start" key="DescriptorPlugin:HashDescriptorManifestExt:range_5_offset"/>
<Range5Size value="0x0" label="Range 5 size" help_text="Range 5 size covers OEM defined unprotected range length" key="DescriptorPlugin:HashDescriptorManifestExt:range_5_size"/>
<Range6Offset value="0x0" label="Range 6 offset" help_text="Range 6 offset covers OEM defined unprotected range start" key="DescriptorPlugin:HashDescriptorManifestExt:range_6_offset"/>
<Range6Size value="0x0" label="Range 6 size" help_text="Range 6 size covers OEM defined unprotected range length" key="DescriptorPlugin:HashDescriptorManifestExt:range_6_size"/>
<Range7Offset value="0x0" label="Range 7 offset" help_text="Range 7 offset covers OEM defined unprotected range start" key="DescriptorPlugin:HashDescriptorManifestExt:range_7_offset"/>
<Range7Size value="0x0" label="Range 7 size" help_text="Range 7 size covers OEM defined unprotected range length" key="DescriptorPlugin:HashDescriptorManifestExt:range_7_size"/>
<Range8Offset value="0x0" label="Range 8 offset" help_text="Range 8 offset covers OEM defined unprotected range start" key="DescriptorPlugin:HashDescriptorManifestExt:range_8_offset"/>
<Range8Size value="0x0" label="Range 8 size" help_text="Range 8 size covers OEM defined unprotected range length" key="DescriptorPlugin:HashDescriptorManifestExt:range_8_size"/>
</ExclusionRanges>
<BootGuardConfiguration label="Boot Guard Configuration">
<BtGuardCpuDebugEnable value="Enabled" value_list="['Enabled', 'Disabled']" label="CPU Debugging" help_text="This setting determines if CPU debug modes will be displayed. When set to 'Yes' CPU debugging is enabled." key="CsePlugin:UEP:BtGuardCpuDebugEnable"/>
<BtGuardBspInitEnable value="Enabled" value_list="['Enabled', 'Disabled']" label="BSP Initialization" help_text="his setting determines bsp behavior when it receives an init signal. when set to 'enabled' (enable is dbi bit = 0). when bsp receives an init. bsp will signal an error to the bss register and enter unrecoverable shutdown (disable is dbi bit = 1)." key="CsePlugin:UEP:BtGuardBspInitEnable"/>
<BtGuardKeyManifestId value="0x0" label="Key Manifest ID" help_text="ODM identifier used during the Key manifest authentication process. This setting is only configurable, and must be non-0, when OEM Public Key Hash is set (See PlatformIntegrity/OemPublicKeyHash)." key="CsePlugin:UEP:BtGuardKeyManifestId"/>
<BtGuardProfileConfig value="Boot Guard Profile 0 - No_FVME" value_list="['Boot Guard Profile 0 - No_FVME', 'Boot Guard Profile 3 - VM', 'Boot Guard Profile 4 - FVE', 'Boot Guard Profile 5 - FVME']" label="Boot Guard Profile Configuration" help_text="This option configures the which boot guard policy profile will be used. Note: all profiles with the exception of profile 0 - fvme support txt being enabled." key="CsePlugin:UEP:BtGuardProfileConfig"/>
</BootGuardConfiguration>
<IntelPttConfiguration label="Intel(R) PTT Configuration">
<SmxSupport value="Enabled" value_list="['Enabled', 'Disabled']" label="SMx State" help_text="" key="CsePlugin:AutoNvars:PttSmxSupport#SmxSupport"/>
<Rsa1KSupport value="Enabled" value_list="['Enabled', 'Disabled']" label="Rsa 1K State" help_text="" key="CsePlugin:AutoNvars:PttSmxSupport#Rsa1KSupport"/>
<PttSupported value="Yes" value_list="['No', 'Yes']" label="Intel(R) PTT Supported" help_text="This setting permanently disables Intel(R) PTT in the firmware image." key="CsePlugin:ConfigRulesNvar:ME_CONF_WRK#PttSupported"/>
<PttPwrUpState value="Enabled" value_list="['Disabled', 'Enabled']" label="Intel(R) PTT initial power-up state" help_text="This setting determines if Intel(R) PTT is enabled on platform power-up." key="CsePlugin:ConfigRulesNvar:ME_CONF_WRK#PttPwrUpState"/>
<PttSupportedFpf value="Yes" value_list="['No', 'Yes']" label="Intel(R) PTT Supported [FPF]" help_text="This setting will permanently disable Intel(R) PTT through platform FPFs. Caution: Using this option will permanently disable Intel(R) PTT on the platform hardware." key="CsePlugin:UEP:PttSupportedFpf"/>
</IntelPttConfiguration>
<TpmOverSpiBusConfiguration label="TPM Over SPI Bus Configuration">
<SpiOverTpmClkFreq value="14MHz" value_list="['14MHz', '25MHz', '48MHz']" label="TPM Clock Frequency" help_text="This setting determines the clock frequency setting to be used for the TPM over SPI bus." key="DescriptorPlugin:PchStraps:PCH_Strap_SPI_STCF"/>
<SpiOverTpmBusEnable value="No" value_list="['No', 'Yes']" label="TPM Over SPI Bus Enabled" help_text="This setting determines the clock frequency setting to be used for the TPM over SPI bus." key="DescriptorPlugin:PchStraps:PCH_Strap_LPC_spi_strap_tos"/>
</TpmOverSpiBusConfiguration>
<BiosGuardConfiguration label="BIOS Guard Configuration">
<BiosGrdProtOvrdEn value="No" value_list="['No', 'Yes']" label="BIOS Guard Protection Override Enabled" help_text="This setting allows BIOS Guard to bypass SPI flash controller protections (i.e. Protected Range Registers and Top Swap)." key="DescriptorPlugin:PchStraps:PCH_Strap_LPC_spi_strap_prr_ts_ovr"/>
</BiosGuardConfiguration>
<TxtConfiguration label="TXT Configuration">
<TxtSupported value="No" value_list="['No', 'Yes']" label="TXT Supported" help_text="This setting determines is enabled for the platform." key="CsePlugin:UEP:TxtSupported"/>
</TxtConfiguration>
<CryptoHardwareSupport label="Crypto Hardware Support">
<CryptoHwSupport value="Yes" value_list="['Yes', 'No']" label="Crypto HW Support" help_text="This setting can be used to disable crypto funtionality. This settings disables all crypto dependent features." key="CsePlugin:AutoNvars:ME_CONF_WRK#CryptoHwSupport"/>
</CryptoHardwareSupport>
<TrustedDeviceSetup label="Trusted Device Setup">
<EnableTDS value="No" value_list="['No', 'Yes']" label="Enable TDS Capabilities" help_text="This setting enables Intel(R) Trusted Device Setup on the platform" key="CsePlugin:AutoNvars:ME_CONF_WRK#EnableTDS"/>
</TrustedDeviceSetup>
<FuSaConfiguration label="FuSa Configuration">
<FuSaPrfTstRepI2CIntrfc value="SMLink0" value_list="['SMBus', 'SMLink0', 'SMLink1']" label="FuSa Proof Tests Reporting I2C Interface" help_text="This setting determines which SMBus interface will be used for FuSa Proof Tests Reporting I2C interface." key="CsePlugin:GBST:FuSaPrfTstRepI2CIntrfc"/>
<FuSaPrfTstMcuI2CAddrs value="0x50" label="FuSa Proof Tests MCU I2C Address" help_text="This setting configures the FuSa Proof Tests I2C MCU address for the platform." key="CsePlugin:GBST:FuSaPrfTstMcuI2CAddrs"/>
<FuSaPrfTestComponents value="0x1780" label="FuSa Proof Test Components" help_text="This setting determines which FuSa tests will be run based on the mask value input.Note: See Firmware Bring-up Guide for valid values." key="CsePlugin:GBST:FuSaPrfTestComponents"/>
</FuSaConfiguration>
</PlatformProtection>
<Icc label="Integrated Clock Controller">
<IccPolicies label="Integrated Clock Controller Policies">
<BootProfile value="Profile 0" value_list="['Profile 0']" label="Boot Profile" help_text="Profile applied during each boot." key="CsePlugin:Icc:BootProfile"/>
<FailsafeBootProfile value="Profile 0" value_list="['Profile 0']" label="Failsafe Boot Profile" help_text="Boot profile used when system instability is detected." key="CsePlugin:Icc:FailsafeBootProfile"/>
<ProfileChangeable value="true" value_list="['false', 'true']" label="Profile Changeable" help_text="True = Allows user to change boot profile via BIOS menu or 3rd party application False = Prevents user from changing boot profile via BIOS or 3rd party application. Note: When false, Failsafe Boot Profile must be the same as Boot Profile." key="CsePlugin:Icc:ProfileChangeable"/>
<Profiles label="Profiles">
<Profile label="Profile">
<Active value="true" value_list="['false', 'true']" label="Profile Active State" help_text="" key="CsePlugin:Icc:0/Active"/>
<ProfileName value="Profile 0" label="Profile Name" help_text="Editable text string stored with the profile for easy identification." key="CsePlugin:Icc:0/ProfileName"/>
<ClockOutputConfiguration label="Clock Output Configuration">
<Sscen value="Enabled" value_list="['Disabled', 'Enabled']" label="SSCEN" help_text="SSC Control for 100MHz Refclock" key="CsePlugin:Icc:0/Sscen"/>
<ClkoutSRC0 value="Enabled" value_list="['Disabled', 'Enabled']" label="SRC0" help_text="Enable/Disable the CLKOUT_SRC0 differential output buffer." key="CsePlugin:Icc:0/ClkoutSRC0"/>
<ClkoutSRC1 value="Enabled" value_list="['Disabled', 'Enabled']" label="SRC1" help_text="Enable/Disable the CLKOUT_SRC1 differential output buffer." key="CsePlugin:Icc:0/ClkoutSRC1"/>
<ClkoutSRC2 value="Disabled" value_list="['Disabled', 'Enabled']" label="SRC2" help_text="Enable/Disable the CLKOUT_SRC2 differential output buffer." key="CsePlugin:Icc:0/ClkoutSRC2"/>
<ClkoutSRC3 value="Enabled" value_list="['Disabled', 'Enabled']" label="SRC3" help_text="Enable/Disable the CLKOUT_SRC3 differential output buffer." key="CsePlugin:Icc:0/ClkoutSRC3"/>
<ClkoutSRC4 value="Disabled" value_list="['Disabled', 'Enabled']" label="SRC4" help_text="Enable/Disable the CLKOUT_SRC4 differential output buffer." key="CsePlugin:Icc:0/ClkoutSRC4"/>
<ClkoutSRC5 value="Disabled" value_list="['Disabled', 'Enabled']" label="SRC5" help_text="Enable/Disable the CLKOUT_SRC5 differential output buffer." key="CsePlugin:Icc:0/ClkoutSRC5"/>
<ClkoutSRC6 value="Disabled" value_list="['Disabled', 'Enabled']" label="SRC6" help_text="Enable/Disable the CLKOUT_SRC6 differential output buffer." key="CsePlugin:Icc:0/ClkoutSRC6"/>
</ClockOutputConfiguration>
<PwrManagementConfiguration label="Power Management Configuration">
<ClkreqMapSRC0 value="GPPC_D5" value_list="['GPPC_D5', 'GPPC_D6', 'GPPC_D7', 'GPPC_D8', 'GPPC_H19', 'GPPC_H23', 'GPPC_F19']" label="SRC0 CLKREQ# Mapping" help_text="Assign the CLKREQ# signal associated with CLKOUT_SRC0. Please note that remapping of any SRC CLKREQ# would require swapping the relevant status of SRC# under Clock Output Configuration to match the remapping." key="CsePlugin:Icc:0/ClkreqMapSRC0"/>
<ClkreqMapSRC1 value="GPPC_D6" value_list="['GPPC_D5', 'GPPC_D6', 'GPPC_D7', 'GPPC_D8', 'GPPC_H19', 'GPPC_H23', 'GPPC_F19']" label="SRC1 CLKREQ# Mapping" help_text="Assign the CLKREQ# signal associated with CLKOUT_SRC1. Please note that remapping of any SRC CLKREQ# would require swapping the relevant status of SRC# under Clock Output Configuration to match the remapping." key="CsePlugin:Icc:0/ClkreqMapSRC1"/>
<ClkreqMapSRC2 value="GPPC_D7" value_list="['GPPC_D5', 'GPPC_D6', 'GPPC_D7', 'GPPC_D8', 'GPPC_H19', 'GPPC_H23', 'GPPC_F19']" label="SRC2 CLKREQ# Mapping" help_text="Assign the CLKREQ# signal associated with CLKOUT_SRC2. Please note that remapping of any SRC CLKREQ# would require swapping the relevant status of SRC# under Clock Output Configuration to match the remapping." key="CsePlugin:Icc:0/ClkreqMapSRC2"/>
<ClkreqMapSRC3 value="GPPC_D8" value_list="['GPPC_D5', 'GPPC_D6', 'GPPC_D7', 'GPPC_D8', 'GPPC_H19', 'GPPC_H23', 'GPPC_F19']" label="SRC3 CLKREQ# Mapping" help_text="Assign the CLKREQ# signal associated with CLKOUT_SRC3. Please note that remapping of any SRC CLKREQ# would require swapping the relevant status of SRC# under Clock Output Configuration to match the remapping." key="CsePlugin:Icc:0/ClkreqMapSRC3"/>
<ClkreqMapSRC4 value="GPPC_H19" value_list="['GPPC_D5', 'GPPC_D6', 'GPPC_D7', 'GPPC_D8', 'GPPC_H19', 'GPPC_H23', 'GPPC_F19']" label="SRC4 CLKREQ# Mapping" help_text="Assign the CLKREQ# signal associated with CLKOUT_SRC4. Please note that remapping of any SRC CLKREQ# would require swapping the relevant status of SRC# under Clock Output Configuration to match the remapping." key="CsePlugin:Icc:0/ClkreqMapSRC4"/>
<ClkreqMapSRC5 value="GPPC_H23" value_list="['GPPC_D5', 'GPPC_D6', 'GPPC_D7', 'GPPC_D8', 'GPPC_H19', 'GPPC_H23', 'GPPC_F19']" label="SRC5 CLKREQ# Mapping" help_text="Assign the CLKREQ# signal associated with CLKOUT_SRC5. Please note that remapping of any SRC CLKREQ# would require swapping the relevant status of SRC# under Clock Output Configuration to match the remapping." key="CsePlugin:Icc:0/ClkreqMapSRC5"/>
<ClkreqMapSRC6 value="GPPC_F19" value_list="['GPPC_D5', 'GPPC_D6', 'GPPC_D7', 'GPPC_D8', 'GPPC_H19', 'GPPC_H23', 'GPPC_F19']" label="SRC6 CLKREQ# Mapping" help_text="Assign the CLKREQ# signal associated with CLKOUT_SRC6. Please note that remapping of any SRC CLKREQ# would require swapping the relevant status of SRC# under Clock Output Configuration to match the remapping." key="CsePlugin:Icc:0/ClkreqMapSRC6"/>
</PwrManagementConfiguration>
</Profile>
</Profiles>
</IccPolicies>
</Icc>
<NetworkingConnectivity label="Networking and Connectivity">
<WiredLanConfiguration label="Wired Lan Configuration">
<LanPhyPwrCtrlGpd11Config value="Enable as LANPHYPC" value_list="['Enable as GPD11', 'Enable as LANPHYPC']" label="LAN PHY Power Control GPD11 Signal Configuration" help_text="This setting allows the user to assign the LAN PHY Power Control signal to GbE or as GDP11. Note: If using Intel(R) Integrated LAN this setting should be set to &quot;&quot;Enable as LANPHYPC&quot;&quot;." key="DescriptorPlugin:PchStraps:PCH_Strap_GPCOM2_gpio_sstrap_gpd_11_lanphypc_sel"/>
<GbeMacSmbAddrs value="0x70" label="GbE MAC SMBus Address" help_text="This setting configures Intel(R) Integrated Wired LAN MAC SMBus address to accept SMBus cycles from the PHY. Note: Recommended setting is 70h." key="DescriptorPlugin:PchStraps:PCH_Strap_CSME_SMS1_GbE_ADDR"/>
<GbeMacSmbAddrsEn value="Yes" value_list="['No', 'Yes']" label="GbE MAC SMBus Address Enabled" help_text="This enables the Intel(R) Integrated Wired LAN MAC SMBus address. Note: This setting must be enabled if using Intel(R) Integrated LAN." key="DescriptorPlugin:PchStraps:PCH_Strap_CSME_SMS1_GBE_EN"/>
<GbePHYSmbAddrs value="0x64" label="GbE PHY SMBus Address" help_text="This is the Intel PHY SMBus address. &lt;br /&gt;This field must be programmed to 64h. &lt;br /&gt;GbE PHY SMBus Address and GbE MAC address have to be programmed to 64h and 70h in &lt;br /&gt;order to ensure proper arbitration of SMBus communication between the Intel integrated MAC and PHY." key="DescriptorPlugin:PchStraps:PCH_Strap_CSME_SMS2_GbE_ADDR"/>
<PhyConnected value="No PHY Connected" value_list="['No PHY Connected', 'PHY on SMBus', 'PHY on SMLink0', 'PHY on SMLink1']" label="PHY Connection" help_text="This selects which SMBus network is used to connect GbE PHY to MAC/PCH." key="DescriptorPlugin:PchStraps:PCH_Strap_GBE_Phy_Connected_PHYCON"/>
<GbePCIePortSelect value="Port8" value_list="['None', 'Port7', 'Port8', 'Port9']" label="GbE PCIe Port Select" help_text="This setting allows customers to configure the PCIe Port that will Intel(R) Integrated LAN will operate on." key="DescriptorPlugin:PchStraps:GbePCIePortSelect"/>
<LanPhyPwrUpTime value="100ms" value_list="['100ms', '50ms']" label="LAN PHY Power Up Time" help_text="This bit determines how long the delay for LAN PHY to power up after de-assertion of &lt;br /&gt;SLP_LAN#" key="DescriptorPlugin:PmcStraps:PMC_Strap_pmc_smip_LAN_PHY_PU_TIME"/>
<LanEnable value="No" value_list="['Yes', 'No']" label="Intel(R) Integrated Wired LAN Enabled" help_text="This setting allows customers to enable / disable Intel(R) Integrated LAN operation over the PCIe Port selected by the GbE PCIe Port Select option." key="DescriptorPlugin:PmcStraps:PMC_Strap_pmc_smip_GBE_DIS_STRAP"/>
<MELanPowerWell value="SLP_LAN#" value_list="['Core Well', 'SUS Well', 'ME Well', 'SLP_LAN#']" label="LAN Power Well" help_text="This setting allows the customer to configure the powerwell that will be used by Intel(R) Integrated LAN. Note: Recommended setting is SLP_LAN#." key="CsePlugin:AutoNvars:ME_CONF_WRK#MELanPowerWell"/>
</WiredLanConfiguration>
<WirelessLanConfiguration label="Wireless Lan Configuration">
<SlpWlanGdp9Config value="Enable as SLP_WLAN#" value_list="['Enable as SLP_WLAN#', 'Enable as GPD9']" label="SLP_WLAN# / GDP9 Signal Configuration" help_text="This setting allows user the to assign the WLAN Power Control signal to WLAN or as GDP9. Note: If using Intel(R) Wireless LAN this setting should be set to &quot;&quot;Enable as SLP_WLAN#&quot;&quot;." key="DescriptorPlugin:PchStraps:PCH_Strap_GPCOM2_gpio_sstrap_gpd_9_slp_wlanb_sel"/>
<CnviWlanCrdEn value="Enabled" value_list="['Enabled', 'Disabled']" label="CNVi WLAN Card Enabled" help_text="This setting determine whether the platform support CNVi based WLAN card or not. &lt;br /&gt;Note: This setting should be set to enabled on either Corporate or Consumer planforms to avoid issues if WLAN card is changed in the future." key="DescriptorPlugin:PmcStraps:PMC_Strap_pmc_smip_CNVI_DIS_STRAP"/>
<MeClinkEnable value="Yes" value_list="['No', 'Yes']" label="Intel(R) ME CLINK Signal Enabled" help_text="This setting allows customers to enable / disable the Wireless LAN CLINK signal through Intel(R) ME firmware. Note: For using Intel(R) vPro Wireless solutions this should be set to Yes." key="CsePlugin:AutoNvars:ME_CONF_WRK#MeClinkEnable"/>
<MEWlanPowerWell value="SLP_WLAN#" value_list="['Disabled', 'Core Well || SLP_S3#', 'Primary Well || SLP_SUS#', 'ME Well || SLP_A#', 'SLP_WLAN#']" label="WLAN Power Well" help_text="This setting allow the customer to configure the powerwell that will be used by Intel(R) wireless lan. note: recommended setting is slp_wlan#" key="CsePlugin:AutoNvars:ME_CONF_WRK#MEWlanPowerWell"/>
</WirelessLanConfiguration>
<TimeSensitiveNetworkingConfiguration label="Time Sensitive Networking Configuration">
<TsnEnabled value="TSN Disabled" value_list="['TSN Enabled', 'TSN Disabled']" label="Time Sensitive Networking" help_text="This setting allows customers to enable / disable Time Sensitive Networking on the platform. &lt;br /&gt;Note: This feature is not applicable for ICP-N." key="DescriptorPlugin:PmcStraps:PMC_Strap_pmc_smip_GBETSN_DIS_STRAP"/>
<TsnGbePortSelect value="None" value_list="['None', 'TSN Port 6', 'TSN Port 7']" label="TSN GbE Port Select" help_text="This setting allows customers to configure the PCIe Port that will the TSN GbE will operate on. &amp;lt;br /&amp;gt;Note: The Intel(R ) Integrated LAN and TSN GbE are mutually exclusive only one of them can be configued." key="DescriptorPlugin:PmcStraps:TsnGbePortSelect"/>
</TimeSensitiveNetworkingConfiguration>
</NetworkingConnectivity>
<InternalPchBuses label="Internal PCH Buses">
<PchTimerConfiguration label="PCH Timer Configuration">
<t573TimingConfig value="1ms" value_list="['100ms', '50ms', '5ms', '1ms']" label="PCH clock output stable to PROCPWRGD high (tPCH45)" help_text="This setting configures the minimum timing from XCK_PLL locked to CPUPWRGD high. For further details see Alder lake Platform Controller Hub EDS." key="DescriptorPlugin:PmcStraps:PMC_Strap_pmc_smip_T573_TIMING"/>
<t1001TimingConfig value="1ms" value_list="['1ms', '5ms', '2ms']" label="PROCPWRGD and SYS_PWROK high to SUS_STAT# de-assertion (tPCH46)" help_text="This setting configures the minimum timing from CPUPWRGD assertion to SUS_STAT#. For further details see Alder Lake Controller Hub EDS." key="DescriptorPlugin:PmcStraps:PMC_Strap_pmc_smip_T1001_TIMING"/>
<OcWdtSsEnable value="OC WDT Disabled" value_list="['OC WDT Disabled', 'OC WDT 3 Second Timeout', 'OC WDT 5 Second Timeout', 'OC WDT 10 Second Timeout', 'OC WDT 15 Second Timeout', 'OC WDT 30 Second Timeout', 'OC WDT 45 Second Timeout', 'OC WDT 60 Second Timeout']" label="Over Clocking Watchdog Self Start Enable" help_text="This setting affect whether the Over Clocking Watchdog Timer is enabled to automatically start on Host power cycle." key="DescriptorPlugin:PmcStraps:PMC_Strap_pmc_smip_OC_WDT_SS_EN"/>
<ApwrokTiming value="2ms" value_list="['2ms', '4ms', '8ms', '15ms']" label="APWROK Timing" help_text="This soft strap determines the timing between the SLP_A# pin de-asserting and the APWROK timer expiration." key="DescriptorPlugin:PmcStraps:PMC_Strap_pmc_smip_APWROK_TIMING"/>
<t36TimerEnable value="Disabled" value_list="['Disabled', 'Enabled']" label="PCIe Power Stable Timer (tPCH33)" help_text="This setting configures the enables / disables the tPCH33 timer. When enabled PCH will count 99ms from PWROK assertion before PLTRST# is de-asserted. Note: The recommended setting is &quot;&quot;Disabled&quot;&quot;" key="DescriptorPlugin:PmcStraps:PMC_Strap_pmc_smip_T36_ENABLE"/>
</PchTimerConfiguration>
<SmbusSmlinkConfiguration label="SMBus / SMLink Configuration">
<SmbAlrtModeConfig value="Enable as GPP_C2" value_list="['Enable as GPP_C2', 'Enable as Intel(R) SMBus ASD']" label="Intel(R) SMBus ASD Mode Configuration" help_text="This setting determines the native mode of operation for the Intel(R) SMBus ASD signal." key="DescriptorPlugin:PchStraps:PCH_Strap_GPCOM4_gpio_sstrap_smbalertb"/>
<SMBusTcoSlaveSelect value="Intel(R) SMBus" value_list="['Intel(R) SMBus', 'SMLink 0']" label="SMBus / SMLink TCO Slave Connection" help_text="This setting configures the TCO Slave connection to ether the Intel(R) SMBus or SMLink0. For further details see Alder Lake Platform Controller Hub EDS." key="DescriptorPlugin:PchStraps:PCH_Strap_CSME_SMT1_TCOSSEL"/>
<SMBusI2cAddress value="0x0" label="Intel(R) SMBus I2C Address" help_text="This setting configures the Intel(R) SMBus I2C Address. Note: This setting is only used for testing purposes. The recommended setting is &quot;&quot;0000000&quot;&quot;" key="DescriptorPlugin:PchStraps:PCH_Strap_CSME_SMT1_I2C_ADDR"/>
<SMBusAsdAddress value="0x0" label="Intel(R) SMBus ASD Address" help_text="This setting configures the Intel(R) SMBus Alert Sending Device Address. For details see Alder Lake SPI Programming guide further details." key="DescriptorPlugin:PchStraps:PCH_Strap_CSME_SMT1_ASD_ADDR"/>
<SMBusMctpAddress value="0x0" label="Intel(R) SMBus MCTP Address" help_text="This setting configures the Intel(R) SMBus MCTP Address. Note: This setting is only used for testing purposes. The default setting is &quot;&quot;0000000&quot;&quot;" key="DescriptorPlugin:PchStraps:PCH_Strap_CSME_SMT1_MCTP_ADDR"/>
<SMBusI2cEnable value="No" value_list="['No', 'Yes']" label="Intel(R) SMBus I2C Address Enabled" help_text="This setting enables / disables the Intel(R) SMBus I2C Address. Note: This setting is only used for testing purposes. The recommended setting is &quot;&quot;No&quot;&quot;" key="DescriptorPlugin:PchStraps:PCH_Strap_CSME_SMT1_I2C_EN"/>
<SMBusAsdEnable value="No" value_list="['No', 'Yes']" label="Intel(R) SMBus ASD Address Enabled" help_text="This setting enables / disables the Intel(R) SMBus Alert Sending Device. For details see Alder Lake SPI Programming guide further details." key="DescriptorPlugin:PchStraps:PCH_Strap_CSME_SMT1_ASD_EN"/>
<SMBusMctpEnable value="No" value_list="['No', 'Yes']" label="Intel(R) SMBus MCTP Address Enabled" help_text="This setting enables / disables the Intel(R) SMBus MCTP Address. Note: This setting is only used for testing purposes. The recommended setting is &quot;&quot;No&quot;&quot;" key="DescriptorPlugin:PchStraps:PCH_Strap_CSME_SMT1_MCTP_EN"/>
<SMBusAsfId value="0x0" label="Intel(R) SMBus Subsystem Vendor and Device ID for ASF" help_text="This setting configures the Intel(R) SMBus Subsystem Vendor and Device ID for ASF. For details see Alder Lake SPI Programming guide further details." key="DescriptorPlugin:PchStraps:PCH_Strap_CSME_SMT1_AUDIDB118"/>
<SLink0Enable value="No" value_list="['No', 'Yes']" label="SMLink0 Enabled" help_text="This setting enables / disables SMLink0 interface. For further details see Alder Lake Platform Controller Hub EDS. Note: If using Intel(R) NFC this setting must be set to &quot;&quot;Yes&quot;&quot;." key="DescriptorPlugin:PchStraps:PCH_Strap_CSME_SMT2_SMTEN"/>
<SLink0I2cAddress value="0x0" label="SMLink0 I2C Address" help_text="This setting configures the SMLink0 I2C Address. &lt;br /&gt;Note: This setting is used as a part of the Intel(R) vPro Thunderbolt(tm) dock configuration." key="DescriptorPlugin:PchStraps:PCH_Strap_CSME_SMT2_I2C_ADDR"/>
<SLink0MctpAddress value="0x0" label="Intel(R) SMLink0 MCTP Address" help_text="This setting configures the Intel(R) SMLink0 MCTP Address. &lt;br /&gt;Note: This setting is only used for testing." key="DescriptorPlugin:PchStraps:PCH_Strap_CSME_SMT2_MCTP_ADDR"/>
<SMLink0I2cEnable value="No" value_list="['No', 'Yes']" label="SMLink0 I2C Address Enabled" help_text="This setting enables / disables the SMLink0 I2C Address. &lt;br /&gt;Note: This setting is used as a part of the Intel(R) vPro Thunderbolt(tm) dock configuration." key="DescriptorPlugin:PchStraps:PCH_Strap_CSME_SMT2_I2C_EN"/>
<SLink0MctpEnable value="No" value_list="['No', 'Yes']" label="Intel(R) SMLink0 MCTP Address Enabled" help_text="This setting enables / disables the Intel(R) SMLink0 MCTP Address. &lt;br /&gt;Note: This setting is only used for testing purposes." key="DescriptorPlugin:PchStraps:PCH_Strap_CSME_SMT2_MCTP_EN"/>
<SLink0freq value="1 MHz" value_list="['100 KHz', '400 KHz', '1 MHz']" label="SMLink0 Frequency" help_text="This setting determines the frequency at which the SMLink0 will operate. Note: The recommended setting is &quot;&quot;1MHz&quot;&quot;" key="DescriptorPlugin:PchStraps:PCH_Strap_CSME_SMT2_SPD"/>
<SLink1Enable value="Yes" value_list="['No', 'Yes']" label="SMLink1 Enabled" help_text="This setting enables / disables SMLink1 interface. For further details see Alder Lake Platform Controller Hub EDS. &lt;br /&gt;Note: This setting must be set to &quot;Yes&quot; if using PCH / MCP Thermal reporting." key="DescriptorPlugin:PchStraps:PCH_Strap_CSME_SMT3_SMTEN"/>
<SLink1GPTargetEnable value="No" value_list="['No', 'Yes']" label="SMLink1 GP Target Address Enabled" help_text="This setting enables / disables SMLink1 GP Target Address interface. For further details see Alder Lake Platform Controller Hub EDS. Note: This setting must be set to &quot;&quot;&quot;&quot;Yes&quot;&quot;&quot;&quot; if using PCH / MCP Thermal reporting." key="DescriptorPlugin:PchStraps:PCH_Strap_CSME_SMT3_SML1GPAEN"/>
<SLink1GPTargetAddress value="0x0" label="SMLink1 GP Target Address" help_text="This setting configures SMLink1 GP Target Address. For further details see Alder Lake LP Platform Controller Hub EDS." key="DescriptorPlugin:PchStraps:PCH_Strap_CSME_SMT3_SML1GPA"/>
<SLink1I2cAddress value="0x0" label="SMLink1 I2C Target Address" help_text="This setting configures SMLink1 I2C Target Address. For further details see Alder Lake LP Platform Controller Hub EDS." key="DescriptorPlugin:PchStraps:PCH_Strap_CSME_SMT3_I2C_ADDR"/>
<SLink1MctpAddress value="0x0" label="SMLink1 MCTP Address" help_text="This setting configures the Intel(R) SMBus MCTP Address. Note: This setting is only used for testing purposes. The default setting is &quot;&quot;0000000&quot;&quot;" key="DescriptorPlugin:PchStraps:PCH_Strap_CSME_SMT3_MCTP_ADDR"/>
<SLink1I2cEnable value="No" value_list="['No', 'Yes']" label="SMLink1 I2C Target Address Enabled" help_text="This setting configures SMLink1 I2C Target Address. For further details see Alder Lake LP or Lewisburg Platform Controller Hub EDS." key="DescriptorPlugin:PchStraps:PCH_Strap_CSME_SMT3_I2C_EN"/>
<SLink1MctpEnable value="No" value_list="['No', 'Yes']" label="SMLink1 MCTP Address Enabled" help_text="This setting enables / disables the Intel(R) SMBus MCTP Address. Note: This setting is only used for testing purposes. The recommended setting is &quot;&quot;No&quot;&quot;" key="DescriptorPlugin:PchStraps:PCH_Strap_CSME_SMT3_MCTP_EN"/>
<SLink1freq value="400 KHz" value_list="['100 KHz', '400 KHz', '1 MHz']" label="SMLink1 Frequency" help_text="This setting determines the frequency at which the SMLink1 will operate. Note: The recommended setting is &quot;&quot;100KHz&quot;&quot;" key="DescriptorPlugin:PchStraps:PCH_Strap_CSME_SMT3_SPD"/>
</SmbusSmlinkConfiguration>
<DmiConfiguration label="DMI Configuration">
<DmiLaneReversal value="No" value_list="['No', 'Yes']" label="DMI Lane Reversal" help_text="This setting allow the DMI Lane signals to be reversed. For further details see Canonlake H / LP Platform Controller Hub EDS." key="DescriptorPlugin:PchStraps:PCH_Strap_DMI_DMI_LR"/>
<DmiPciPortStagger value="Yes" value_list="['No', 'Yes']" label="DMI Port Staggering Enabled" help_text="This setting configures DMI for Port Staggering. For further details see Canonlake LP Platform Controller Hub EDS." key="DescriptorPlugin:PchStraps:PCH_Strap_FIA_PSE"/>
</DmiConfiguration>
<OpiDmiConfiguration label="OPI / DMI Configuration">
<OpiLinkSpeed value="4 GT/s" value_list="['2 GT/s', '4 GT/s']" label="OPI / DMI Link Speed" help_text="This setting configures the OPI Link Speed. For further details see Canonlake PCH EDS." key="DescriptorPlugin:PchStraps:PCH_Strap_DMI_OPDMI_TLS"/>
<OpiLinkWidth value="8 Lanes" value_list="['1 Lane', '2 Lanes', '4 Lanes', '8 Lanes']" label="OPI / DMI Link Width" help_text="This setting configures the OPI Link Width. For further details see Canonlake PCH EDS." key="DescriptorPlugin:PchStraps:PCH_Strap_DMI_OPDMI_LW"/>
<OpiLinkVoltage value="0.95 Volts" value_list="['0.85 Volts', '0.95 Volts', '1.05 Volts']" label="OPI /DMI Link Voltage" help_text="This setting configures the OPI Link Voltage. For further details see Alder Lake PCH EDS." key="DescriptorPlugin:PchStraps:PCH_Strap_DMI_OPD_LVO"/>
</OpiDmiConfiguration>
<EspiConfiguration label="eSPI Configuration">
<EspiEcBusfreq value="20MHz" value_list="['20MHz', '25MHz', '33MHz', '50MHz']" label="eSPI / EC Bus Frequency" help_text="Indicates the maximum frequency of the eSPI bus that is supported by the eSPI Master and platform configuration (trace length, number of Slaves, etc.). The actual frequency of the eSPI bus will be the minimum of this field and the Slave's maximum frequency advertised in its General Capabilities register." key="DescriptorPlugin:PchStraps:PCH_Strap_SPI_ec_max_freq"/>
<EspiEcCrcCheckEnable value="Yes" value_list="['Yes', 'No']" label="eSPI / EC CRC Check Enabled" help_text="This setting enables CRC checking on eSPI Slave 0 channel." key="DescriptorPlugin:PchStraps:PCH_Strap_SPI_ec_crcchk_dis"/>
<EspiEcMaxIoMode value="Single, Dual and Quad" value_list="['Single', 'Single and Dual', 'Single and Quad', 'Single, Dual and Quad']" label="eSPI / EC Maximum I/O Mode" help_text="Indicates the maximum IO Mode (Single/Dual/Quad) of the eSPI bus that is supported by the eSPI &lt;br /&gt;Master and specific platform configuration. The actual IO Mode of the eSPI bus will be the minimum &lt;br /&gt;of this field and the Slave's maximum IO Mode advertised in its General Capabilities register." key="DescriptorPlugin:PchStraps:PCH_Strap_SPI_ec_max_io_mode"/>
<EspiEcSlvAtchdFlshMor value="Single Outstanding Request" value_list="['Single Outstanding Request', 'Multiple Outstanding Requests']" label="eSPI / EC Slave Attached Flash Multiple Outstanding Requests Enable" help_text="This setting enabled multiple outstanding requests for the eSPI / EC Slave Attached Flash device." key="DescriptorPlugin:PchStraps:PCH_Strap_SPI_ec_safch_mor_en"/>
<EspiEcSlvAtchdFlshOoo value="In-Order SAF Requests" value_list="['In-Order SAF Requests', 'Out-of-Order SAF Requests']" label="eSPI / EC Slave Attached Flash Channel OOO Enable" help_text="This setting enables Out or Order requests on the eSPI / EC Slave Attached Flash device." key="DescriptorPlugin:PchStraps:PCH_Strap_SPI_ec_safch_ooo_en"/>
<EspiEcMaxOutReqMstrFlCh value="2" value_list="['2', '1']" label="eSPI / EC Max Outstanding Request for Master Attached Flash Channel" help_text="This setting determines the Maximum outstanding requests on the eSPI / EC Master Attached Flash Channel." key="DescriptorPlugin:PchStraps:PCH_Strap_SPI_ec_mafch_mor"/>
</EspiConfiguration>
</InternalPchBuses>
<Power label="Power">
<PlatformPower label="Platform Power">
<SlpS3Gdp4Config value="Enable as SLP_S3#" value_list="['Enable as SLP_S3#', 'Enable as GPD4']" label="SLP_S3# / GPD4 Signal Configuration" help_text="This setting allows the user to assign the SLP_S3# Power Control signal as SLP_S3# or as GDP4. For further details see Canonlake H / LP Platform Controller Hub EDS." key="DescriptorPlugin:PchStraps:PCH_Strap_GPCOM2_gpio_sstrap_gpd_4_slp_s3b_sel"/>
<SlpS4Gdp5Config value="Enable as SLP_S4#" value_list="['Enable as SLP_S4#', 'Enable as GPD5']" label="SLP_S4# / GPD5 Signal Configuration" help_text="This setting allows the user to assign the SLP_S4# Power Control signal as SLP_S4# or as GDP5. For further details see Canonlake H / LP Platform Controller Hub EDS." key="DescriptorPlugin:PchStraps:PCH_Strap_GPCOM2_gpio_sstrap_gpd_5_slp_s4b_sel"/>
<SlpAGpd6Config value="Enable as SLP_A#" value_list="['Enable as SLP_A#', 'Enable as GPD6']" label="SLP_A# / GPD6 Signal Configuration" help_text="This setting allows the user to assign the SLP_A# Power Control signal as SLP_A# or as GDP6. For further details see Canonlake H / LP Platform Controller Hub EDS." key="DescriptorPlugin:PchStraps:PCH_Strap_GPCOM2_gpio_sstrap_gpd_6_slp_ab_sel"/>
<SlpS5Gdp10Config value="Enable as SLP_S5#" value_list="['Enable as SLP_S5#', 'Enable as GPD10']" label="SLP_S5# / GPD10 Signal Configuration" help_text="This setting allows the user to assign the SLP_S5# Power Control signal as SLP_S5# or as GDP10. For further details see Canonlake H / LP Platform Controller Hub EDS." key="DescriptorPlugin:PchStraps:PCH_Strap_GPCOM2_gpio_sstrap_gpd_10_slp_s5b_sel"/>
<SlpS0TunnelDis value="Disabled" value_list="['Enabled', 'Disabled']" label="SLP_S0# Tunnel" help_text="This setting Enables / Disables the tunneling of the SLP_S0# pin over ESPI to the EC when in ESPI mode." key="DescriptorPlugin:PmcStraps:PMC_Strap_pmc_smip_SLP_S0_TUNNEL_DIS"/>
</PlatformPower>
<DeepSx label="Deep Sx">
<DeepSxSupportEnable value="Yes" value_list="['No', 'Yes']" label="Deep Sx Enabled" help_text="This setting enables / disables support for Deep Sx operation. For further details see Alder Lake Platform Controller Hub EDS. Note: Support for Deep Sx is board design dependent." key="DescriptorPlugin:PmcStraps:PMC_Strap_pmc_smip_DEEPSX_PLT_CFG"/>
</DeepSx>
<PchThermalReporting label="PCH Thermal Reporting">
<PchThrmlRprtngEn value="Yes" value_list="['Yes', 'No']" label="Thermal Power Reporting Enabled" help_text="This setting enabled a once-per-second timer interrupt is enabled which triggers firmware to report power and temperature information as enabled by configuration registers. &lt;br /&gt;Note: When this setting is disabled ensure that the once-per-second timer interrupt associated with this feature is also disabled." key="DescriptorPlugin:PmcStraps:PMC_Strap_pmc_smip_THERM_PWR_REP_DIS"/>
</PchThermalReporting>
</Power>
<IntegratedSensorHub label="Integrated Sensor Hub">
<IntegratedSensorHub label="Integrated Sensor Hub">
<IshSupported value="No" value_list="['Yes', 'No']" label="Integrated Sensor Hub Supported" help_text="This setting allows customers to enable / disable ISH on the platform." key="DescriptorPlugin:PmcStraps:PMC_Strap_pmc_smip_ISH_DIS_STRAP"/>
<IshPowerUpState value="Disabled" value_list="['Disabled', 'Enabled']" label="Integrated Sensor Hub Initial Power State" help_text="This setting allows customers to determine the power up state for ISH." key="CsePlugin:ConfigRulesNvar:ME_CONF_WRK#IshPowerUpState"/>
</IntegratedSensorHub>
<IshImage label="ISH Image">
<InputFile value="" label="ISH Input File" help_text="Path to your ISH firmware binary file." key="CsePlugin:ISH:InputFile_path"/>
<Length value="0x48000" label="Integrated Sensor Hub Length" help_text="Total size (in bytes) of the ISH code partition including reserved space. It is recommended to be at least 256kb." key="CsePlugin:ISH:Length"/>
</IshImage>
<IshData label="ISH Data">
<PdtBinary value="" label="ISH PDT Binary File" help_text="Path to your PDT binary file." key="CsePlugin:AutoNvars:IshPdt#IshPdtBinary"/>
</IshData>
</IntegratedSensorHub>
<Camera label="Camera">
<IPUSecurity label="IPU Security Configuration">
<PrivacyFeatureControlDisabled value="true" value_list="['false', 'true']" label="Camera privacy feature control disabled" help_text="This NVAR enables/disables the camera privacy. Enabling this NVAR means that the Camera privacy GPIO Pin value is used to mask/unmask all cameras’ data from being used" key="CsePlugin:AutoNvars:IunitPrivacyControl#PrivacyFeatureControlDisabled"/>
<SecureTouch value="Disabled" value_list="['Disabled', 'Enabled']" label="Secure Touch" help_text="When set, CAMERA_MASK register bits per CSI port are used to mask the data of cameras. When cleared, camera data is not masked. " key="CsePlugin:AutoNvars:IUnitOemCfg#SecureTouch"/>
<FWSecureMode value="Enabled" value_list="['Disabled', 'Enabled']" label="FW Secure Mode" help_text="If enabled, access blockers in IS and PS are enabled, and FW is read from IMR. Must be enabled for FW authentication flow and execution of authenticated FW." key="CsePlugin:AutoNvars:IUnitOemCfg#FWSecureMode"/>
<SecureTouchCameraMask value="0xFF" label="Secure Touch and Camera Mask" help_text="Camera mask bits per CSI port. When SECURE_TOUCH is set each set bit masks a CSI port for secure touch. When SECURE_TOUCH is cleared this register has no impact on the CSI ports." key="CsePlugin:AutoNvars:IUnitOemCfg#SecureTouchCameraMask"/>
</IPUSecurity>
<IPUDebug label="IPU Debug">
<RomTraceEnable value="Enabled" value_list="['Disabled', 'Enabled']" label="IPU Debugging Enabled" help_text="If enabled, IPU Debugging is enabled, otherwise internal setup is checked to see if the IPU Debugging feature should be enabled or not." key="CsePlugin:AutoNvars:IUnitOemCfg#RomTraceEnable"/>
</IPUDebug>
<IPUPhy label="IPU PHY">
<PortConfigurationFor8LSBLanes value="0x0" label="Port Configuration For 8 LSB Lanes" help_text="When SW DRIVER CONTROLS PORT CONFIGURATION is cleared this determines the port configuration mapping between the lower 8 MIPI lanes and the CSI receiver ports the lanes can connect to.:
Bits[3:0] determine the configuration of Port A:
0x0: port is disabled
0x4: X1 (ICL only)
0x5: X2 (ICL only)
Others: reserved
Bits[8:4] determine the configuration of Port B:
0x0: port is disabled
Others: reserved
Bits[10:9] determine the configuration of Port C:
0x0: port is disabled
0x2: X1
Others: reserved
Bits[13:11] determine the configuration of Port D:
0x0: port is disabled
0x5: X2
0x7: X4
Others: reserved" key="CsePlugin:AutoNvars:IUnitOemCfg#PortConfigurationFor8LSBLanes"/>
<PortConfigurationFor8MSBLanes value="0x0" label="Port Configuration For 8 MSB Lanes" help_text="When SW DRIVER CONTROLS PORT CONFIGURATION is cleared this determines the port configuration mapping between the upper 8 MIPI lanes and the CSI receiver ports the lanes can connect to.:
Bits[3:0] determine the configuration of Port A:
0x0: port is disabled
0x4: X1
0x5: X2
Others: reserved
Bits[8:4] determine the configuration of Port B:
0x0: port is disabled
0x9: X2
Others: reserved
Bits[10:9] determine the configuration of Port C:
0x0: port is disabled
0x2: X1
Others: reserved
Bits[13:11] determine the configuration of Port D:
0x0: port is disabled
0x5: X2
0x7: X4
Others: reserved" key="CsePlugin:AutoNvars:IUnitOemCfg#PortConfigurationFor8MSBLanes"/>
</IPUPhy>
</Camera>
<Debug label="Debug">
<Idlm label="IDLM">
<IdlmFile value="" label="IDLM Binary" help_text="This allows an IDLM binary to be merged into output image built by Intel (R) FIT" key="CsePlugin:IDLM:input_file_path"/>
</Idlm>
<DelayedAuthenticationModeConfiguration label="Delayed Authentication Mode Configuration">
<DelayedAuthMode value="No" value_list="['No', 'Yes']" label="Delayed Authentication Mode Enabled" help_text="This setting enables Delayed Authentication Mode on the platform." key="CsePlugin:AutoNvars:Dam#DelayedAuthMode"/>
</DelayedAuthenticationModeConfiguration>
<IntelTraceHubTechnology label="Intel(R) Trace Hub Technology">
<RomTraceEmergencyModeEn value="No" value_list="['No', 'Yes']" label="Intel(R) Trace Hub Emergency Mode Enabled" help_text="When enabled, Intel(R) ME programs Intel(R) Trace Hub to send debug traces over DCI OOB without target configuration from the Intel(R) System Studio tool. Note: This is intended for debug purposes only and should not be used in &quot;the&quot; shipping configuration." key="DescriptorPlugin:PchStraps:PCH_Strap_CSME_CSE_TRACEHUB_EMERGENCY_EN"/>
<PmcDbgMsgsEnable value="Yes" value_list="['No', 'Yes']" label="PMC Hub Debug Messages Enabled" help_text="This setting enables PMC FW trace messages to Intel(R) &lt;br /&gt;Trace Hub - When set to Yes, enables trace messages." key="DescriptorPlugin:PmcStraps:PMC_Strap_pmc_smip_STH_DBG_MSG_EN"/>
<UnlockToken value="" label="Unlock Token" help_text="This allows to enable debug capabilities using Secure Token binary file.&amp;#13;&amp;#10;Note: Need to move to separated 'Secure Debug' group." key="CsePlugin:UTOK:input_file_path"/>
<IntelTrcHubBinary value="" label="Intel(R) Trace Hub Binary" help_text="This is the Intel(R) trace hub configuration file. which will be applied by intel me to configure Intel(R) trace hub. use this option to restore Intel(R) trace hub configuration when necessary." key="CsePlugin:AutoNvars:NorthPeakDebug#IntelTrcHubBinary"/>
<RomTraceFiltering value="" label="Intel(R) Trace Hub Filtering" help_text="This setting allows a user input binary for filtering of output messages for Intel(R) Trace Hub" key="CsePlugin:AutoNvars:TraceHubFiltering#RomTraceFiltering"/>
</IntelTraceHubTechnology>
<IntelMeFirmwareDebuggingOverrides label="Intel(R) ME Firmware Debugging Overrides">
<MERomBypassEnable value="No" value_list="['No', 'Yes']" label="Firmware ROM Bypass" help_text="This setting enables / disables firmware ROM bypass. Note: This setting only has affect when the firmware being used has ROM Bypass code present." key="DescriptorPlugin:PchStraps:PCH_Strap_CSME_CSE_CSE_ROM_Bypass_Enable_Softstrap"/>
<MeRstBehavior value="Intel(R) ME Alternate image boot" value_list="['Intel(R) ME Alternate image boot', 'Intel(R) ME will Halt']" label="Intel(R) ME Reset Behavior" help_text="This setting determines Intel(R) ME behavior when boot image errors are encountered. &lt;br /&gt; &lt;br /&gt;Warning: This setting should be used for debug purposes only." key="DescriptorPlugin:PchStraps:PCH_Strap_CSME_CSE_SSS_AVOID_RESETS_ON_BAD_PATHS"/>
<AfsIdleReclaim value="Yes" value_list="['Yes', 'No']" label="AFS Idle Flash Reclaim Enabled" help_text="This controls enabling / disabling of Intel(R) ME AFS Idle flash reclaim capabilities. &lt;br /&gt; &lt;br /&gt;Note: This setting should be used for debug purposes only." key="DescriptorPlugin:PchStraps:PCH_Strap_CSME_CSE_AFS_Reclaim_Dis"/>
<DbgOverridePreProdSi value="0x0" label="Debug Override Pre-Production Silicon" help_text="Allows the OEM to control FW features to assist with pre-production platform debugging. This control has no effect if used on production silicon. Note: Certain options will do not work when the descriptor is locked (See FW Bring-up Guide for setting details)." key="CsePlugin:AutoNvars:KernFixedData#DbgOverridePreProdSi"/>
<DbgOverrideProdSi value="0x0" label="Debug Override Production Silicon" help_text="Allows the OEM to control FW features to assist with production platform debugging. Note: Certain options will do not work when the descriptor is locked (See FW Bring-up Guide for setting details)." key="CsePlugin:AutoNvars:KernFixedData#DbgOverrideProdSi"/>
</IntelMeFirmwareDebuggingOverrides>
<DirectConnectInterfaceConfiguration label="Direct Connect Interface Configuration">
<DciDbcEnable value="No" value_list="['No', 'Yes']" label="Intel(R) DCI DbC Interface Enabled" help_text="This setting enables / disables the Intel(R) DCI DbC interface. &lt;br /&gt;Note: Applies only before End of Manufacture." key="DescriptorPlugin:PchStraps:PCH_Strap_CSME_CSE_DCI_EN"/>
<Usb1DciOobEnable value="Yes" value_list="['Yes', 'No']" label="DCI OOB over USB3 Port1 Enabled" help_text="This setting determines if the USB port being enabled for DCI OOB. If disabled it will block DCI OOB connection. &lt;br /&gt;Note: This setting will be grayed out if USB3 / PCIe Combo Port 0 under the Flex I/O tab is set to 'PCIe (or GbE)'" key="DescriptorPlugin:PchStraps:PCH_Strap_EXI_PTSS_PORT0"/>
<Usb2DciOobEnable value="No" value_list="['Yes', 'No']" label="DCI OOB over USB3 Port2 Enabled" help_text="This setting determines if the USB port being enabled for DCI OOB. If disabled it will block DCI OOB connection. &lt;br /&gt;Note: This setting will be grayed out if USB3 / PCIe Combo Port 1 under the Flex I/O tab is set to 'PCIe (or GbE)'" key="DescriptorPlugin:PchStraps:PCH_Strap_EXI_PTSS_PORT1"/>
<Usb3DciOobEnable value="Yes" value_list="['Yes', 'No']" label="DCI OOB over USB3 Port3 Enabled" help_text="This setting determines if the USB port being enabled for DCI OOB. If disabled it will block DCI OOB connection. &lt;br /&gt;Note: This setting will be grayed out if USB3 / PCIe Combo Port 2 under the Flex I/O tab is set to 'PCIe (or GbE)'" key="DescriptorPlugin:PchStraps:PCH_Strap_EXI_PTSS_PORT2"/>
<Usb4DciOobEnable value="No" value_list="['Yes', 'No']" label="DCI OOB over USB3 Port4 Enabled" help_text="This setting determines if the USB port being enabled for DCI OOB. If disabled it will block DCI OOB connection. &lt;br /&gt;Note: This setting will be grayed out if USB3 / PCIe Combo Port 3 under the Flex I/O tab is set to 'PCIe (or GbE)'" key="DescriptorPlugin:PchStraps:PCH_Strap_EXI_PTSS_PORT3"/>
</DirectConnectInterfaceConfiguration>
<EspiFeatureOverrides label="eSPI Feature Overrides">
<EspiEcLowFreqOvrd value="No" value_list="['Yes', 'No']" label="eSPI / EC Low Frequency Debug Override" help_text="When enabled this setting will divide eSPI clock frequency by 8. &lt;br /&gt;Note: This setting should only be used for debugging purposes. Leaving this setting enable will impact eSPI performance." key="DescriptorPlugin:PchStraps:PCH_Strap_SPI_espi_freq_divby8_ovrd"/>
</EspiFeatureOverrides>
<EarlyUsb2DbcOverType-AConfiguration label="Early USB2 DBC over Type-A Configuration">
<Usb2DbcPortEn value="No USB2 Ports" value_list="['USB2 Port 1', 'USB2 Port 2', 'USB2 Port 3', 'USB2 Port 4', 'USB2 Port 5', 'USB2 Port 6', 'USB2 Port 7', 'USB2 Port 8', 'USB2 Port 9', 'USB2 Port 10', 'No USB2 Ports']" label="USB2 DbC port enable" help_text="This setting dedicates USB2 STD-A port for USB2 DbC exclusively. It blocks functional traffic on this port and USB.DbC traffic on all other ports, including USB Type-C ports. &lt;br /&gt;Note: These fields do not apply to USB Type-C ports. Early USB2 DBC over Type-A Configuration" key="DescriptorPlugin:DbCStraps:DbC_Strap_CSME_USB2_DbC_port_enable"/>
<Usb3DbcPortEn value="No USB3 Ports" value_list="['USB3 Port 1', 'USB3 Port 2', 'USB3 Port 3', 'USB3 Port 4', 'USB3 Port 5', 'USB3 Port 6', 'No USB3 Ports']" label="USB Connectors Associated USB3 Port enable" help_text="This setting disables USB3 lanes on STD-A port for USB2.DbC. &lt;br /&gt;Note: Default is DISABLED" key="DescriptorPlugin:DbCStraps:DbC_Strap_CSME_USB3_DbC_port_enable"/>
<EnEarlyUsb2DbcCon value="No" value_list="['No', 'Yes']" label="Enable early USB2 DbC connection" help_text="This setting enables a delay during Intel(R) ME FW bring-up to allow USB2 DbC connection to be established." key="DescriptorPlugin:DbCStraps:DbC_Strap_CSME_Early_USB_DbC_ME_Boot_Stall_Enable"/>
</EarlyUsb2DbcOverType-AConfiguration>
</Debug>
<CpuStraps label="CPU Straps">
<CpuStraps label="CPU Straps">
<Mipi124RailSrcPlat value="No" value_list="['No', 'Yes']" label="MIPI 1.24 Rail Sourced from Platform" help_text="This setting determines if MIPI 1.24 Rail Source is provided by the platform. &lt;br /&gt;Yes = MIPI 1.24 Rail provided by Platform &lt;br /&gt;No = MIPI 1.24 Rail not provided by Platform" key="DescriptorPlugin:PmcStraps:PMC_Strap_pmc_smip_VCC_MIPI_DPHY_LP_IS_1p24"/>
<HyperThreadingDisable value="No" value_list="['No', 'Yes']" label="Disable Hyperthreading" help_text="This setting control enabling / disabling of Hyper threading. &lt;br /&gt;Note: This strap is intended for debugging purposed only. See BIOS Spec for more details on enabling / disabling Hyper threading" key="DescriptorPlugin:CpuStraps:CPU_Strap_SMT_Disable"/>
<NumActiveBigCore value="All Cores Active" value_list="['All Cores Active', '1 Core Active', '2 Cores Active', '3 Cores Active', '4 Cores Active', '5 Cores Active']" label="Number of Active Big Cores" help_text="This setting controls the number of active Big Core processors. &lt;br /&gt;Note: This strap is intended for debugging purposed only. See BIOS Spec for more details on enabling / disabling processor cores." key="DescriptorPlugin:CpuStraps:CPU_Strap_Num_Of_Big_Cores"/>
<BistInit value="No" value_list="['No', 'Yes']" label="BIST Initialization" help_text="This setting determines if BIST will be run at platform reset after BIOS requested actions. &lt;br /&gt;Note: This strap is intended for debugging purposed only." key="DescriptorPlugin:CpuStraps:CPU_Strap_BIST"/>
<FlexRatio value="0x0" label="Flex Ratio" help_text="This setting controls the maximum processor non-turbo ratio. &lt;br /&gt;Note: This strap is intended for debugging purposed only. See BIOS Spec for more details on maximum processor non-turbo ratio configuration." key="DescriptorPlugin:CpuStraps:CPU_Strap_FlexRatio"/>
<CpuMaxFreqBoot value="Yes" value_list="['No', 'Yes']" label="Processor Boot at P1 Frequency" help_text="Processor Boot at P1 Frequency" key="DescriptorPlugin:CpuStraps:CPU_Strap_Fast_wakeup"/>
<JtagPwrDisable value="No JTAG Power on C10 and Lower" value_list="['No JTAG Power on C10 and Lower', 'JTAG Power on C10 and Lower']" label="JTAG Power Disable" help_text="This setting determines if JTAG power will be maintained on C10 or lower power states. &lt;br /&gt;Note: This strap is intended for debugging purposed only." key="DescriptorPlugin:CpuStraps:CPU_Strap_JTAG_PowerGate_DISABLE"/>
<NumActiveSmallCores value="All Cores Active" value_list="['All Cores Active', '1 Core Active', '2 Cores Active', '3 Cores Active', '4 Cores Active', '5 Cores Active', '6 Cores Active', '7 Cores Active', '8 Cores Active']" label="Number of Active Small Cores" help_text="This setting controls the number of active small core processors. &lt;br /&gt;Note: If the Number of Active Big Cores setting is configured to a specific number of individual cores active and the Number of Active Small Cores is configured to All Cores Active the Small core processors will be disabled. &lt;br /&gt;Note: This strap is intended for debugging purposed only. See BIOS Spec for more details on enabling / disabling processor cores." key="DescriptorPlugin:CpuStraps:CPU_Strap_NUM_OF_ATOM_CORES"/>
<Vcc105vCpuSrc value="VCC 1.05v CPU Source PCH" value_list="['VCC 1.05v CPU Source PCH', 'VCC 1.05v CPU source Platform Rail']" label="VCC 1.05v CPU Source" help_text="This setting determines where the VCC 1.05v CPU Sourced from." key="DescriptorPlugin:CpuStraps:CPU_Strap_VCC1p05_CPU_SOURCE_IS_PLATFORM"/>
<Vccp105CpuPg value="VCCP 1.05 CPU PG present" value_list="['VCCP 1.05 CPU PG Not present', 'VCCP 1.05 CPU PG present']" label="VCCP 1.05 CPU PG Exists" help_text="This enables VCCP 1.05 CPU Power Gating capabilities if present on the platform." key="DescriptorPlugin:CpuStraps:CPU_Strap_VCCP105_CPU_POWERGATE_EXISTS"/>
<CpuPciePeg10En value="Yes" value_list="['Yes', 'No']" label="Processor PCIe 10 enabled" help_text="This setting determines if PCIe PEG 10 is enabled or disabled." key="DescriptorPlugin:CpuStraps:CPU_Strap_DEV1FN0_DISABLE"/>
<VccinAuxLevelLp value="1.8v" value_list="['1.8v', '1.65v']" label="VCCIN Aux Level LP" help_text="This setting determines the VCCIN Aux Level LP voltage. &lt;br /&gt;Note: Y based MCPs this setting can be configured to 1.65v. On all MCP types set to 1.8v." key="DescriptorPlugin:CpuStraps:CPU_Strap_VCCIN_AUX_LP_LEVEL"/>
<VccAuxImonEn value="No" value_list="['Yes', 'No']" label="VCCIN AUX IMON Enabled" help_text="This setting determines if VCCIN AUX IMON is enabled." key="DescriptorPlugin:CpuStraps:CPU_Strap_VCCIN_AUX_IMON_DISABLED"/>
<IaSvidAddress value="0x0" label="IA SVID Address" help_text="This setting determines the IA SVID address. See Processor EDS for details. &lt;br /&gt;Note: This strap should be left at the recommended default setting." key="DescriptorPlugin:CpuStraps:CPU_Strap_IA_SVID_Address"/>
<IaVrType value="SVID" value_list="['SVID', 'Fixed VR']" label="IA VR Type" help_text="This setting determines the IA core VR type. See Processor EDS for details." key="DescriptorPlugin:CpuStraps:CPU_Strap_IA_VR_Type"/>
<GtsSvidAddress value="0x1" label="GT_S SVID Address" help_text="This setting determines the GT slice SVID Address. See Processor EDS for details." key="DescriptorPlugin:CpuStraps:CPU_Strap_GT_SVID_Address"/>
<GtsVrType value="SVID" value_list="['SVID', 'Fixed VR']" label="GT_S VR Type" help_text="This setting determines the GT slice domain VR type. See Processor EDS for details." key="DescriptorPlugin:CpuStraps:CPU_Strap_GT_VR_Type"/>
<IaVrOffsetVid value="Yes" value_list="['No', 'Yes']" label="IA SVID VR Offset Enabled" help_text="Enables/disables a voltage offset for the IA VR allowing voltage levels to exceed 1.52V. &lt;br /&gt;The setting should always be set to Enabled." key="DescriptorPlugin:CpuStraps:CPU_Strap_SET_IA_VR_OFFSET_VID"/>
<VccInAuxImonSvidAddSel value="VCCINAUX on 0xD" value_list="['VCCINAUX on 0xD', 'VCCINAUX on 0x4']" label="VCCIN Aux IMON SVID Address Select" help_text="This setting determines which SVID address will be used to read the VccInAux rail current. &lt;br /&gt;Note: ADL-M only." key="DescriptorPlugin:CpuStraps:CPU_Strap_VCCINAUX_IMON_SVID_ADDRESS_SEL"/>
<VccSaSvidVrAddr value="0x0" label="VCCSA SVID VR Address" help_text="This setting determines the VCCSA SVID VR Address for the platform. &lt;br /&gt;Note: ADL-M only." key="DescriptorPlugin:CpuStraps:CPU_Strap_VCCSA_SVID_Address"/>
<VccSaSvidVrType value="SVID" value_list="['SVID', 'Fixed VR']" label="VCCSA SVID VR Type" help_text="This setting determines the VCCSA SVID VR Type. See Processor EDS for details. &lt;br /&gt;Note: ADL-M only." key="DescriptorPlugin:CpuStraps:CPU_Strap_VCCSA_VR_Type"/>
<PlatformImonDisable value="Enabled" value_list="['Enabled', 'Disabled']" label="Platform IMON" help_text="This strap should be left at the recommended default setting." key="DescriptorPlugin:CpuStraps:CPU_Strap_Psys_Disable"/>
<P2toP2TranClkDomain value="P2 to P2 Asyc to PCLK" value_list="['P2 to P2 Sync to PCLK', 'P2 to P2 Asyc to PCLK']" label="P2 to P2 Transition Clock Domain" help_text="This setting controls the P2 to P2 Transition Clock Domain." key="DescriptorPlugin:CpuStraps:CPU_Strap_PEG10_P2TP2TCD"/>
</CpuStraps>
</CpuStraps>
<FlexIO label="Flex IO">
<PcieLaneReversalConfiguration label="PCIe Lane Reversal Configuration">
<PCIeCtrl1LnReversal value="No" value_list="['No', 'Yes']" label="PCIe Controller 1 Lane Reversal Enabled" help_text="This setting allows the PCIe lanes on Controller 1 to be reversed. For further details see Canonlake H / LP Platform Controller Hub EDS." key="DescriptorPlugin:PchStraps:PCH_Strap_PCIE0_LNREV"/>
<PCIeCtrl2LnReversal value="No" value_list="['No', 'Yes']" label="PCIe Controller 2 Lane Reversal Enabled" help_text="This setting allows the PCIe lanes on Controller 2 to be reversed. For further details see Canonlake H / LP Platform Controller Hub EDS." key="DescriptorPlugin:PchStraps:PCH_Strap_PCIE1_LNREV"/>
<PCIeCtrl3LnReversal value="No" value_list="['No', 'Yes']" label="PCIe Controller 3 Lane Reversal Enabled" help_text="This setting allows the PCIe lanes on Controller 3 to be reversed. For further details see Canonlake H / LP Platform Controller Hub EDS." key="DescriptorPlugin:PchStraps:PCH_Strap_PCIE2_LNREV"/>
</PcieLaneReversalConfiguration>
<PciePortConfiguration label="PCIe Port Configuration">
<PCIeController1Config value="4x1" value_list="['4x1', '1x2, 2x1', '2x2', '1x4']" label="PCIe Controller 1 (Port 1-4)" help_text="This setting controls PCIe Port configurations for PCIe Controller 1. For further details see Alder Lake P / M Platform Controller Hub EDS." key="DescriptorPlugin:PchStraps:PCH_Strap_PCIE0_RPCFG"/>
<PCIeController2Config value="1x4" value_list="['4x1', '1x2, 2x1', '2x2', '1x4']" label="PCIe Controller 2 (Port 5-8)" help_text="This setting controls PCIe Port configurations for PCIe Controller 2. For further details see Alder Lake P / M Platform Controller Hub EDS." key="DescriptorPlugin:PchStraps:PCH_Strap_PCIE1_RPCFG"/>
<PCIeController3Config value="4x1" value_list="['4x1', '1x2, 2x1', '2x2', '1x4']" label="PCIe Controller 3 (Port 9-12)" help_text="This setting controls PCIe Port configurations for PCIe Controller 3. For further details see Alder Lake P / M Platform Controller Hub EDS." key="DescriptorPlugin:PchStraps:PCH_Strap_PCIE2_RPCFG"/>
</PciePortConfiguration>
<SataPcieComboPortConfiguration label="SATA / PCIe Combo Port Configuration">
<SataPCIeComboPort0 value="SATA" value_list="['GPIO Polarity PCIe', 'GPIO Polarity SATA', 'SATA', 'PCIe', 'Disabled']" label="SATA / PCIe Combo Port 0" help_text="This setting configures the PCIe port to operate as either PCIe Port 11 or SATA Port 0. For further details on Flex I/O see Alder Lake Platform Controller Hub EDS." key="DescriptorPlugin:PchStraps:PCH_Strap_FIA_LOSL10"/>
<SataPCIeComboPort1 value="PCIe" value_list="['GPIO Polarity PCIe', 'GPIO Polarity SATA', 'SATA', 'PCIe', 'Disabled']" label="SATA / PCIe Combo Port 1" help_text="This setting configures the PCIe port to operate as either PCIe Port 12 or SATA Port 1. For further details on Flex I/O see Alder Lake Platform Controller Hub EDS." key="DescriptorPlugin:PchStraps:PCH_Strap_FIA_LOSL11"/>
</SataPcieComboPortConfiguration>
<Usb3PortConfiguration label="USB3 Port Configuration">
<USB3Port1SpdCap value="USB 3.1 Gen1" value_list="['USB 3.1 Gen1', 'USB 3.1 Gen2']" label="USB3 Port 1 Speed Capability" help_text="This setting determines the USB3 Port 1 speed capabilities." key="DescriptorPlugin:PchStraps:PCH_Strap_USBX_PORT_SPEED_CAP_STRAP_PORT1"/>
<USB3Port2SpdCap value="USB 3.1 Gen1" value_list="['USB 3.1 Gen1', 'USB 3.1 Gen2']" label="USB3 Port 2 Speed Capability" help_text="This setting determines the USB3 Port 2 speed capabilities." key="DescriptorPlugin:PchStraps:PCH_Strap_USBX_PORT_SPEED_CAP_STRAP_PORT2"/>
<USB3Port3SpdCap value="USB 3.1 Gen1" value_list="['USB 3.1 Gen1', 'USB 3.1 Gen2']" label="USB3 Port 3 Speed Capability" help_text="This setting determines the USB3 Port 3 speed capabilities." key="DescriptorPlugin:PchStraps:PCH_Strap_USBX_PORT_SPEED_CAP_STRAP_PORT3"/>
<USB3Port4SpdCap value="USB 3.1 Gen1" value_list="['USB 3.1 Gen1', 'USB 3.1 Gen2']" label="USB3 Port 4 Speed Capability" help_text="This setting determines the USB3 Port 4 speed capabilities." key="DescriptorPlugin:PchStraps:PCH_Strap_USBX_PORT_SPEED_CAP_STRAP_PORT4"/>
<USB3Port1IntSpdSel value="USB3.1 Gen1 LBPM" value_list="['USB3.1 Gen1 LBPM', 'USB3.1 Gen2 Skip LBPM']" label="USB3 Port 1 Initialization Speed Select" help_text="This setting determines USB3 Port 1 speed during platform power-up. &lt;br /&gt;Note: When configured to USB 3.1 Gen1 the port will also preform carry on LBPM if USB 3.1 is Gen2 enabled." key="DescriptorPlugin:PchStraps:PCH_Strap_USBX_INIT_PORT_SPEED_SELECT_STRAP_PORT1"/>
<USB3Port2IntSpdSel value="USB3.1 Gen1 LBPM" value_list="['USB3.1 Gen1 LBPM', 'USB3.1 Gen2 Skip LBPM']" label="USB3 Port 2 Initialization Speed Select" help_text="This setting determines USB3 Port 2 speed during platform power-up. &lt;br /&gt;Note: When configured to USB 3.1 Gen1 the port will also preform carry on LBPM if USB 3.1 is Gen2 enabled." key="DescriptorPlugin:PchStraps:PCH_Strap_USBX_INIT_PORT_SPEED_SELECT_STRAP_PORT2"/>
<USB3Port3IntSpdSel value="USB3.1 Gen1 LBPM" value_list="['USB3.1 Gen1 LBPM', 'USB3.1 Gen2 Skip LBPM']" label="USB3 Port 3 Initialization Speed Select" help_text="This setting determines USB3 Port 3 speed during platform power-up. &lt;br /&gt;Note: When configured to USB 3.1 Gen1 the port will also preform carry on LBPM if USB 3.1 is Gen2 enabled." key="DescriptorPlugin:PchStraps:PCH_Strap_USBX_INIT_PORT_SPEED_SELECT_STRAP_PORT3"/>
<USB3Port4IntSpdSel value="USB3.1 Gen1 LBPM" value_list="['USB3.1 Gen1 LBPM', 'USB3.1 Gen2 Skip LBPM']" label="USB3 Port 4 Initialization Speed Select" help_text="This setting determines USB3 Port 4 speed during platform power-up. &lt;br /&gt;Note: When configured to USB 3.1 Gen1 the port will also preform carry on LBPM if USB 3.1 is Gen2 enabled." key="DescriptorPlugin:PchStraps:PCH_Strap_USBX_INIT_PORT_SPEED_SELECT_STRAP_PORT4"/>
<USB3Prt1ConTypeSel value="Type A / Type C" value_list="['Type C', 'Type A / Type C', 'Express Card / M.2 S2']" label="USB3 Port 1 Connector Type Select" help_text="This setting configures the physical connector type to be used for USB 3.0 / 3.1 Port 1." key="DescriptorPlugin:PchStraps:PCH_Strap_USBX_ESS_CONNECTOR_TYPE_STRAP_PORT1"/>
<USB3Prt2ConTypeSel value="Type A / Type C" value_list="['Type C', 'Type A / Type C', 'Express Card / M.2 S2']" label="USB3 Port 2 Connector Type Select" help_text="This setting configures the physical connector type to be used for USB 3.0 / 3.1 Port 2." key="DescriptorPlugin:PchStraps:PCH_Strap_USBX_ESS_CONNECTOR_TYPE_STRAP_PORT2"/>
<USB3Prt3ConTypeSel value="Type A / Type C" value_list="['Type C', 'Type A / Type C', 'Express Card / M.2 S2']" label="USB3 Port 3 Connector Type Select" help_text="This setting configures the physical connector type to be used for USB 3.0 / 3.1 Port 3." key="DescriptorPlugin:PchStraps:PCH_Strap_USBX_ESS_CONNECTOR_TYPE_STRAP_PORT3"/>
<USB3Prt4ConTypeSel value="Type A / Type C" value_list="['Type C', 'Type A / Type C', 'Express Card / M.2 S2']" label="USB3 Port 4 Connector Type Select" help_text="This setting configures the physical connector type to be used for USB 3.0 / 3.1 Port 4." key="DescriptorPlugin:PchStraps:PCH_Strap_USBX_ESS_CONNECTOR_TYPE_STRAP_PORT4"/>
<USB3PCIeComboPort0 value="USB3" value_list="['Disabled', 'USB3', 'PCIe']" label="USB3 / PCIe Combo Port 0" help_text="This setting configures the PCIe port to operate as either PCIe Port 0 or USB3 Port 1. For further details on Flex I/O see AlderLake Platform Controller Hub EDS. &lt;br /&gt;Note: This setting will be grayed out if DCI BSSB over USB3 Port1 Enabled is set to 'yes" key="DescriptorPlugin:PchStraps:PCH_Strap_FIA_LOSL0"/>
<USB3PCIeComboPort1 value="PCIe" value_list="['Disabled', 'USB3', 'PCIe']" label="USB3 / PCIe Combo Port 1" help_text="This setting configures the PCIe port to operate as either PCIe Port 2 or USB3 Port 2. For further details on Flex I/O see Alderlake Platform Controller Hub EDS. &lt;br /&gt;Note: This setting will be grayed out if DCI BSSB over USB3 Port2 Enabled is set to 'yes" key="DescriptorPlugin:PchStraps:PCH_Strap_FIA_LOSL1"/>
<USB3PCIeComboPort2 value="USB3" value_list="['Disabled', 'USB3', 'PCIe']" label="USB3 / PCIe Combo Port 2" help_text="This setting configures the PCIe port to operate as either PCIe Port 3 or USB3 Port 3. For further details on Flex I/O see Alder Lake LP Platform Controller Hub EDS. &lt;br /&gt;Note: This setting will be grayed out if DCI BSSB over USB3 Port3 Enabled is set to 'yes'." key="DescriptorPlugin:PchStraps:PCH_Strap_FIA_LOSL2"/>
<USB3PCIeComboPort3 value="PCIe" value_list="['Disabled', 'USB3', 'PCIe']" label="USB3 / PCIe Combo Port 3" help_text="This setting configures the PCIe port to operate as either PCIe Port 4 or USB3 Port 4. For further details on Flex I/O see Alder Lake Platform Controller Hub EDS. &lt;br /&gt;Note: This setting will be grayed out if DCI BSSB over USB3 Port4 Enabled is set to 'yes'." key="DescriptorPlugin:PchStraps:PCH_Strap_FIA_LOSL3"/>
</Usb3PortConfiguration>
<Usb2PortConfiguration label="USB2 Port Configuration">
<USB2Prt1ConTypeSel value="Type A / Type C" value_list="['Type A / Type C', 'Express Card / M.2 S2']" label="USB2 Port 1 Connector Type Select" help_text="This setting configures the physical connector type to be used for USB2 Port 1." key="DescriptorPlugin:PchStraps:PCH_Strap_USBX_USB2_CONNECTOR_TYPE_STRAP_PORT1"/>
<USB2Prt2ConTypeSel value="Type C" value_list="['Type A / Type C', 'Express Card / M.2 S2']" label="USB2 Port 2 Connector Type Select" help_text="This setting configures the physical connector type to be used for USB2 Port 2." key="DescriptorPlugin:PchStraps:PCH_Strap_USBX_USB2_CONNECTOR_TYPE_STRAP_PORT2"/>
<USB2Prt3ConTypeSel value="Type C" value_list="['Type A / Type C', 'Express Card / M.2 S2']" label="USB2 Port 3 Connector Type Select" help_text="This setting configures the physical connector type to be used for USB2 Port 3." key="DescriptorPlugin:PchStraps:PCH_Strap_USBX_USB2_CONNECTOR_TYPE_STRAP_PORT3"/>
<USB2Prt4ConTypeSel value="Type A / Type C" value_list="['Type A / Type C', 'Express Card / M.2 S2']" label="USB2 Port 4 Connector Type Select" help_text="This setting configures the physical connector type to be used for USB2 Port 4." key="DescriptorPlugin:PchStraps:PCH_Strap_USBX_USB2_CONNECTOR_TYPE_STRAP_PORT4"/>
<USB2Prt5ConTypeSel value="Type A / Type C" value_list="['Type A / Type C', 'Express Card / M.2 S2']" label="USB2 Port 5 Connector Type Select" help_text="This setting configures the physical connector type to be used for USB2 Port 5." key="DescriptorPlugin:PchStraps:PCH_Strap_USBX_USB2_CONNECTOR_TYPE_STRAP_PORT5"/>
<USB2Prt6ConTypeSel value="Type A / Type C" value_list="['Type A / Type C', 'Express Card / M.2 S2']" label="USB2 Port 6 Connector Type Select" help_text="This setting configures the physical connector type to be used for USB2 Port 6." key="DescriptorPlugin:PchStraps:PCH_Strap_USBX_USB2_CONNECTOR_TYPE_STRAP_PORT6"/>
<USB2Prt7ConTypeSel value="Type A / Type C" value_list="['Type A / Type C', 'Express Card / M.2 S2']" label="USB2 Port 7 Connector Type Select" help_text="This setting configures the physical connector type to be used for USB2 Port 7." key="DescriptorPlugin:PchStraps:PCH_Strap_USBX_USB2_CONNECTOR_TYPE_STRAP_PORT7"/>
<USB2Prt8ConTypeSel value="Type A / Type C" value_list="['Type A / Type C', 'Express Card / M.2 S2']" label="USB2 Port 8 Connector Type Select" help_text="This setting configures the physical connector type to be used for USB2 Port 8." key="DescriptorPlugin:PchStraps:PCH_Strap_USBX_USB2_CONNECTOR_TYPE_STRAP_PORT8"/>
<USB2Prt9ConTypeSel value="Type A / Type C" value_list="['Type A / Type C', 'Express Card / M.2 S2']" label="USB2 Port 9 Connector Type Select" help_text="This setting configures the physical connector type to be used for USB2 Port 9." key="DescriptorPlugin:PchStraps:PCH_Strap_USBX_USB2_CONNECTOR_TYPE_STRAP_PORT9"/>
<USB2Prt10ConTypeSel value="Express Card / M.2 S2" value_list="['Type A / Type C', 'Express Card / M.2 S2']" label="USB2 Port 10 Connector Type Select" help_text="This setting configures the physical connector type to be used for USB2 Port 10." key="DescriptorPlugin:PchStraps:PCH_Strap_USBX_USB2_CONNECTOR_TYPE_STRAP_PORT10"/>
</Usb2PortConfiguration>
<Type-CSubsystemConfiguration label="NPHY Configuration">
<TcssPortEnMask value="0xB" label="Type-C Subsystem Port Enable Mask" help_text="This setting determines the Type-C Subsystem Port Enable Mask." key="DescriptorPlugin:CpuStraps:CPU_Strap_TCSS_PORT_EN_MASK_STRAP"/>
<TypeCPort1Config value="No Restrictions" value_list="['No Restrictions', 'DP Fixed Connection', 'No Thunderbolt']" label="Type-C Port 1 Configuration" help_text="This setting determines the configuration of Type-C Port 1." key="DescriptorPlugin:CpuStraps:CPU_Strap_PFIX1"/>
<TypeCPort2Config value="No Restrictions" value_list="['No Restrictions', 'DP Fixed Connection', 'No Thunderbolt']" label="Type-C Port 2 Configuration" help_text="This setting determines the configuration of Type-C Port 2." key="DescriptorPlugin:CpuStraps:CPU_Strap_PFIX2"/>
<TypeCPort3Config value="No Restrictions" value_list="['No Restrictions', 'DP Fixed Connection', 'No Thunderbolt']" label="Type-C Port 3 Configuration" help_text="This setting determines the configuration of Type-C Port 3." key="DescriptorPlugin:CpuStraps:CPU_Strap_PFIX3"/>
<TypeCPort4Config value="DP Fixed Connection" value_list="['No Restrictions', 'DP Fixed Connection', 'No Thunderbolt']" label="Type-C Port 4 Configuration" help_text="This setting determines the configuration of Type-C Port 4." key="DescriptorPlugin:CpuStraps:CPU_Strap_PFIX4"/>
<TypecPort1SpdCap value="USB 3.1 Gen1" value_list="['USB 3.1 Gen1', 'USB 3.1 Gen2']" label="Type-C Port 1 Speed Capability" help_text="This setting determines the Type-C Port 1 speed capabilities." key="DescriptorPlugin:CpuStraps:CPU_Strap_xHCI_PORT_SPEED_CAP_STRAP_PORT1"/>
<TypecPort2SpdCap value="USB 3.1 Gen1" value_list="['USB 3.1 Gen1', 'USB 3.1 Gen2']" label="Type-C Port 2 Speed Capability" help_text="This setting determines the Type-C Port 2 speed capabilities." key="DescriptorPlugin:CpuStraps:CPU_Strap_xHCI_PORT_SPEED_CAP_STRAP_PORT2"/>
<TypecPort3SpdCap value="USB 3.1 Gen1" value_list="['USB 3.1 Gen1', 'USB 3.1 Gen2']" label="Type-C Port 3 Speed Capability" help_text="This setting determines the Type-C Port 3 speed capabilities." key="DescriptorPlugin:CpuStraps:CPU_Strap_xHCI_PORT_SPEED_CAP_STRAP_PORT3"/>
<TypecPort4SpdCap value="USB 3.1 Gen1" value_list="['USB 3.1 Gen1', 'USB 3.1 Gen2']" label="Type-C Port 4 Speed Capability" help_text="This setting determines the Type-C Port 4 speed capabilities." key="DescriptorPlugin:CpuStraps:CPU_Strap_xHCI_PORT_SPEED_CAP_STRAP_PORT4"/>
<TypecPort1IntSpdSel value="USB3.1 Gen1 LBPM" value_list="['USB3.1 Gen1 LBPM', 'USB3.1 Gen2 Skip LBPM']" label="Type-C Port 1 Initialization Speed Select" help_text="This setting determines Type-C Port 1 speed during platform power-up. &lt;br /&gt;Note: When configured to USB 3.1 Gen1 the port will also preform carry on LBPM if USB 3.1 is Gen2 enabled." key="DescriptorPlugin:CpuStraps:CPU_Strap_xHCI_INIT_PORT_SPEED_SELECT_STRAP_PORT1"/>
<TypecPort2IntSpdSel value="USB3.1 Gen1 LBPM" value_list="['USB3.1 Gen1 LBPM', 'USB3.1 Gen2 Skip LBPM']" label="Type-C Port 2 Initialization Speed Select" help_text="This setting determines Type-C Port 2 speed during platform power-up. &lt;br /&gt;Note: When configured to USB 3.1 Gen1 the port will also preform carry on LBPM if USB 3.1 is Gen2 enabled." key="DescriptorPlugin:CpuStraps:CPU_Strap_xHCI_INIT_PORT_SPEED_SELECT_STRAP_PORT2"/>
<TypecPort3IntSpdSel value="USB3.1 Gen1 LBPM" value_list="['USB3.1 Gen1 LBPM', 'USB3.1 Gen2 Skip LBPM']" label="Type-C Port 3 Initialization Speed Select" help_text="This setting determines Type-C Port 3 speed during platform power-up. &lt;br /&gt;Note: When configured to USB 3.1 Gen1 the port will also preform carry on LBPM if USB 3.1 is Gen2 enabled." key="DescriptorPlugin:CpuStraps:CPU_Strap_xHCI_INIT_PORT_SPEED_SELECT_STRAP_PORT3"/>
<TypecPort4IntSpdSel value="USB3.1 Gen1 LBPM" value_list="['USB3.1 Gen1 LBPM', 'USB3.1 Gen2 Skip LBPM']" label="Type-C Port 4 Initialization Speed Select" help_text="This setting determines Type-C Port 4 speed during platform power-up. &lt;br /&gt;Note: When configured to USB 3.1 Gen1 the port will also preform carry on LBPM if USB 3.1 is Gen2 enabled." key="DescriptorPlugin:CpuStraps:CPU_Strap_xHCI_INIT_PORT_SPEED_SELECT_STRAP_PORT4"/>
<TypecPort1ConTypeSel value="Type C" value_list="['Type C', 'Type A', 'Express Card / M.2 S2']" label="Type-C Port 1 Connector Type Select" help_text="This setting configures the physical connector type to be used for Type-C Port 1." key="DescriptorPlugin:CpuStraps:CPU_Strap_xHCI_ESS_CONNECTOR_TYPE_STRAP_PORT1"/>
<TypecPort2ConTypeSel value="Type C" value_list="['Type C', 'Type A', 'Express Card / M.2 S2']" label="Type-C Port 2 Connector Type Select" help_text="This setting configures the physical connector type to be used for Type-C Port 2." key="DescriptorPlugin:CpuStraps:CPU_Strap_xHCI_ESS_CONNECTOR_TYPE_STRAP_PORT2"/>
<TypecPort3ConTypeSel value="Type C" value_list="['Type C', 'Type A', 'Express Card / M.2 S2']" label="Type-C Port 3 Connector Type Select" help_text="This setting configures the physical connector type to be used for Type-C Port 3." key="DescriptorPlugin:CpuStraps:CPU_Strap_xHCI_ESS_CONNECTOR_TYPE_STRAP_PORT3"/>
<TypecPort4ConTypeSel value="Type C" value_list="['Type C', 'Type A', 'Express Card / M.2 S2']" label="Type-C Port 4 Connector Type Select" help_text="This setting configures the physical connector type to be used for Type-C Port 4." key="DescriptorPlugin:CpuStraps:CPU_Strap_xHCI_ESS_CONNECTOR_TYPE_STRAP_PORT4"/>
<XdciSplitDieConfig value="xDCI Split Die Enabled" value_list="['xDCI Split Die Enabled', 'xDCI Split Die Disabled']" label="xDCI Split Die Configuration" help_text="This setting determines if xDCI Split die configuration is enabled / disabled on the platform." key="DescriptorPlugin:CpuStraps:CPU_Strap_xDCI_SPLIT_DIE_XDCI_UFP_SM_PRESENT"/>
<IomBinaryFile value="TCSS/IOM/IOM_20.000b.0.0_preprod.bin" label="IO Manageability Engine Binary File" help_text="This loads the Type-C Subsystem IO Manageability Engine binary that will be merged into the output image generated by the Intel(R) FIT tool." key="CsePlugin:IOM:IomBinaryFile_path"/>
<PhyBinaryFile value="NPHY/ADLP_NPHY_14.502.307.8011.bin" label="NPHY Binary File" help_text="This loads the Type-C Subsystem PHY binary that will be merged into the output image generated by the Intel(R) FIT tool." key="CsePlugin:NPHY:PhyBinaryFile_path"/>
<TbtBinaryFile value="TCSS/TBT/TBT_ADL_J0_rev10_signed.bin" label="Thunderbolt(TM)/USB4(TM) Binary File" help_text="This loads the Type-C Subsystem Thunderbolt(TM)/USB4(TM) binary that will be merged into the output image generated by the Intel(R) FIT tool." key="CsePlugin:TBT:TbtBinaryFile_path"/>
<TcssPartialUpdateEn value="Disabled" value_list="['Disabled', 'Enabled']" label="Tcss - Partial Update Enabled" help_text="This setting enables partial update for TCSS partitions" key="CsePlugin:AutoNvars:TCSS_PartialUpdate#TcssPartialUpdateEn"/>
<IomOemConfigDataFile value="" label="IO Manageability Engine OEM configuration Binary File" help_text="This loads the Type-C Subsystem IO Manageability Engine OEM Configuration binary that will be written to the OEM config data section." key="CsePlugin:AutoNvars:IOM_MG_CFG_DATA#IomOemConfigDataFile"/>
</Type-CSubsystemConfiguration>
<ThunderboltConfiguration label="Thunderbolt Configuration">
<TboltEnable value="No" value_list="['No', 'Yes']" label="Thunderbolt Enable" help_text="This setting determines if the Thunderbolt interface is enabled on the platform." key="DescriptorPlugin:CpuStraps:CPU_Strap_TCSS_TBT_EN_STRAP"/>
</ThunderboltConfiguration>
<UfsConfiguration label="UFS Configuration">
<UfsEnable value="No" value_list="['Yes', 'No']" label="UFS Enabled" help_text="This setting enables UFS Controllers 1 and 2." key="DescriptorPlugin:PmcStraps:UfsEnable"/>
<UfsCont1Config value="None" value_list="['None', 'X1', 'X2']" label="UFS Controller 1" help_text="This setting configures UFS Controller 1 for either x1 or x2 mode." key="DescriptorPlugin:PmcStraps:UfsCont1Config"/>
<UfsCont2Config value="None" value_list="['None', 'X1', 'X2']" label="UFS Controller 2" help_text="This setting configures UFS Controller 2 for either x1 or x2 mode." key="DescriptorPlugin:PmcStraps:UfsCont2Config"/>
</UfsConfiguration>
<PowerDelivery_PdControllerConfiguration label="Power Delivery PD Controller Configuration">
<RetimerPg value="No" value_list="['No', 'Yes']" label="Re-timer Power Gating Enabled" help_text="Indicates whether platform Re-timer power gating is enabled." key="DescriptorPlugin:PmcStraps:PMC_Strap_pmc_smip_Re_timer_Power_Gating_Enabled"/>
<TypeCPort1Mode value="Yes" value_list="['No', 'Yes']" label="Type-C port 1 Enabled" help_text="Indicates whether the associated Type-C port is enabled." key="DescriptorPlugin:PmcStraps:PMC_Strap_pmc_smip_PD0_Type_C_Port_Enabled"/>
<TypeCPort1RetimerEnabled value="Yes" value_list="['No', 'Yes']" label="Type-C Port 1 Re-Timer Present" help_text="Indicates whether a re-timer is present for the associated Type-C port." key="DescriptorPlugin:PmcStraps:PMC_Strap_pmc_smip_PD0_Re_timer_Present"/>
<TypeCPort1RetimerConfig value="No" value_list="['No', 'Yes']" label="Type-C Port 1 Re-timer Configuration Enabled" help_text="Indicates whether the associated re-timer requires configuration. Enabled = configuration done via PMC; Disable = configuration done via PD Controller." key="DescriptorPlugin:PmcStraps:PMC_Strap_pmc_smip_PD0_Re_timer_Configuration_Enabled"/>
<TypeCPort1SmbusAddr value="0x46" label="Type C Port 1 SMBus Address" help_text="SMBus address for the associated type C port" key="DescriptorPlugin:PmcStraps:PMC_Strap_pmc_smip_PD0_Type_C_Port_SMBus_Address"/>
<USB2PortForTypeCPort1 value="USB2 Port 2" value_list="['USB2 Port 1', 'USB2 Port 2', 'USB2 Port 3', 'USB2 Port 4', 'USB2 Port 5', 'USB2 Port 6', 'USB2 Port 7', 'USB2 Port 8', 'USB2 Port 9', 'USB2 Port 10']" label="USB2 Port Number associated for Type-C Port 1" help_text="USB2 port number for the associated Type-C port" key="DescriptorPlugin:PmcStraps:PMC_Strap_pmc_smip_PD0_USB2_Port_Number_for_Type_C_Port"/>
<USB3PortForTypeCPort1 value="Type-C Port 1" value_list="['Type-C Port 1', 'Type-C Port 2', 'Type-C Port 3', 'Type-C Port 4']" label="USB3 Port Number associated for Type-C Port 1" help_text="USB3 port number for the associated Type-C port" key="DescriptorPlugin:PmcStraps:PMC_Strap_pmc_smip_PD0_USB3_Port_Number_for_Type_C_Port"/>
<TypeCPort2Mode value="Yes" value_list="['No', 'Yes']" label="Type-C port 2 Enabled" help_text="Indicates whether the associated Type-C port is enabled" key="DescriptorPlugin:PmcStraps:PMC_Strap_pmc_smip_PD1_Type_C_Port_Enabled"/>
<TypeCPort2RetimerEnabled value="Yes" value_list="['No', 'Yes']" label="Type-C Port 2 Re-Timer Present" help_text="Indicates whether a re-timer is present for the associated Type-C port." key="DescriptorPlugin:PmcStraps:PMC_Strap_pmc_smip_PD1_Re_timer_Present"/>
<TypeCPort2RetimerConfig value="No" value_list="['No', 'Yes']" label="Type-C Port 2 Re-timer Configuration Enabled" help_text="Indicates whether the associated re-timer requires configuration. Enabled = configuration done via PMC; Disable = configuration done via PD Controller" key="DescriptorPlugin:PmcStraps:PMC_Strap_pmc_smip_PD1_Re_timer_Configuration_Enabled"/>
<TypeCPort2SMBusAddr value="0x4E" label="Type-C Port 2 SMBus Address" help_text="SMBus address for the associated Type-C port" key="DescriptorPlugin:PmcStraps:PMC_Strap_pmc_smip_PD1_Type_C_Port_SMBus_Address"/>
<USB2PortForTypeCPort2 value="USB2 Port 3" value_list="['USB2 Port 1', 'USB2 Port 2', 'USB2 Port 3', 'USB2 Port 4', 'USB2 Port 5', 'USB2 Port 6', 'USB2 Port 7', 'USB2 Port 8', 'USB2 Port 9', 'USB2 Port 10']" label="USB2 Port Number associated for Type-C Port 2" help_text="USB2 port number for the associated Type-C port" key="DescriptorPlugin:PmcStraps:PMC_Strap_pmc_smip_PD1_USB2_Port_Number_for_Type_C_Port"/>
<USB3PortForTypeCPort2 value="Type-C Port 2" value_list="['Type-C Port 1', 'Type-C Port 2', 'Type-C Port 3', 'Type-C Port 4']" label="USB3 Port Number associated for Type-C Port 2" help_text="USB3 port number for the associated Type-C port" key="DescriptorPlugin:PmcStraps:PMC_Strap_pmc_smip_PD1_USB3_Port_Number_for_Type_C_Port"/>
<TypeCPort3Mode value="No" value_list="['No', 'Yes']" label="Type-C port 3 Enabled" help_text="Indicates whether the associated Type-C port is enabled" key="DescriptorPlugin:PmcStraps:PMC_Strap_pmc_smip_PD2_Type_C_Port_Enabled"/>
<TypeCPort3RetimerEnabled value="No" value_list="['No', 'Yes']" label="Type-C Port 3 Re-Timer Present" help_text="Indicates whether a re-timer is present for the associated Type-C port." key="DescriptorPlugin:PmcStraps:PMC_Strap_pmc_smip_PD2_Re_timer_Present"/>
<TypeCPort3RetimerConfig value="No" value_list="['No', 'Yes']" label="Type-C Port 3 Re-timer Configuration Enabled" help_text="Indicates whether the associated re-timer requires configuration. Enabled = configuration done via PMC; Disable = configuration done via PD Controller" key="DescriptorPlugin:PmcStraps:PMC_Strap_pmc_smip_PD2_Re_timer_Configuration_Enabled"/>
<TypeCPort3SmbusAddr value="0x52" label="Type-C Port 3 SMBus Address" help_text="SMBus address for the associated Type-C port" key="DescriptorPlugin:PmcStraps:PMC_Strap_pmc_smip_PD2_Type_C_Port_SMBus_Address"/>
<USB2PortForTypeCPort3 value="USB2 Port 3" value_list="['USB2 Port 1', 'USB2 Port 2', 'USB2 Port 3', 'USB2 Port 4', 'USB2 Port 5', 'USB2 Port 6', 'USB2 Port 7', 'USB2 Port 8', 'USB2 Port 9', 'USB2 Port 10']" label="USB2 Port Number associated for Type-C Port 3" help_text="USB2 port number for the associated Type-C port" key="DescriptorPlugin:PmcStraps:PMC_Strap_pmc_smip_PD2_USB2_Port_Number_for_Type_C_Port"/>
<USB3PortForTypeCPort3 value="Type-C Port 3" value_list="['Type-C Port 1', 'Type-C Port 2', 'Type-C Port 3', 'Type-C Port 4']" label="USB3 Port Number associated for Type-C Port 3" help_text="USB3 port number for the associated Type-C port" key="DescriptorPlugin:PmcStraps:PMC_Strap_pmc_smip_PD2_USB3_Port_Number_for_Type_C_Port"/>
<TypeCPort4Mode value="No" value_list="['No', 'Yes']" label="Type-C port 4 Enabled" help_text="Indicates whether the associated Type-C port is enabled" key="DescriptorPlugin:PmcStraps:PMC_Strap_pmc_smip_PD3_Type_C_Port_Enabled"/>
<TypeCPort4RetimerEnabled value="No" value_list="['No', 'Yes']" label="Type-C Port 4 Re-Timer Present" help_text="Indicates whether a re-timer is present for the associated Type-C port." key="DescriptorPlugin:PmcStraps:PMC_Strap_pmc_smip_PD3_Re_timer_Present"/>
<TypeCPort4RetimerConfig value="No" value_list="['No', 'Yes']" label="Type-C Port 4 Re-timer Configuration Enabled" help_text="Indicates whether the associated re-timer requires configuration. Enabled = configuration done via PMC; Disable = configuration done via PD Controller" key="DescriptorPlugin:PmcStraps:PMC_Strap_pmc_smip_PD3_Re_timer_Configuration_Enabled"/>
<TypeCPort4SmbusAddr value="0x53" label="Type-C Port 4 SMBus Address" help_text="SMBus address for the associated Type-C port" key="DescriptorPlugin:PmcStraps:PMC_Strap_pmc_smip_PD3_Type_C_Port_SMBus_Address"/>
<USB2PortForTypeCPort4 value="USB2 Port 5" value_list="['USB2 Port 1', 'USB2 Port 2', 'USB2 Port 3', 'USB2 Port 4', 'USB2 Port 5', 'USB2 Port 6', 'USB2 Port 7', 'USB2 Port 8', 'USB2 Port 9', 'USB2 Port 10']" label="USB2 Port Number associated for Type-C Port 4" help_text="USB2 port number for the associated Type-C port" key="DescriptorPlugin:PmcStraps:PMC_Strap_pmc_smip_PD3_USB2_Port_Number_for_Type_C_Port"/>
<USB3PortForTypeCPort4 value="Type-C Port 4" value_list="['Type-C Port 1', 'Type-C Port 2', 'Type-C Port 3', 'Type-C Port 4']" label="USB3 Port Number associated for Type-C Port 4" help_text="USB3 port number for the associated Type-C port" key="DescriptorPlugin:PmcStraps:PMC_Strap_pmc_smip_PD3_USB3_Port_Number_for_Type_C_Port"/>
</PowerDelivery_PdControllerConfiguration>
</FlexIO>
<Gpio label="GPIO">
<GpioVccioVoltageControl label="GPIO VCCIO Voltage Control">
<HdaVoltSelect value="1.8Volts" value_list="['3.3Volts', '1.8Volts']" label="Intel(R) HD Audio Voltage Select" help_text="This setting controls configures the VCCIO voltage for all of the Intel(R) HD Audio GPIO pins." key="DescriptorPlugin:PchStraps:PCH_Strap_GPCOM5_gpio_sstrap_vccio_gpp_r_select"/>
<GppC0voltSelect value="3.3Volts" value_list="['3.3Volts', '1.8Volts']" label="GPP_C0 Individual Voltage Select" help_text="This setting controls the VCCIO voltage for the GPP_C0 GPIO pin." key="DescriptorPlugin:PchStraps:PCH_Strap_GPCOM4_gpio_sstrap_vccio_pad_gppc_c0"/>
<GppC1voltSelect value="3.3Volts" value_list="['3.3Volts', '1.8Volts']" label="GPP_C1 Individual Voltage Select" help_text="This setting controls the VCCIO voltage for the GPP_C1 GPIO pin." key="DescriptorPlugin:PchStraps:PCH_Strap_GPCOM4_gpio_sstrap_vccio_pad_gppc_c1"/>
<GppC2voltSelect value="3.3Volts" value_list="['3.3Volts', '1.8Volts']" label="GPP_C2 Individual Voltage Select" help_text="This setting controls the VCCIO voltage for the GPP_C2 GPIO pin." key="DescriptorPlugin:PchStraps:PCH_Strap_GPCOM4_gpio_sstrap_vccio_pad_gppc_c2"/>
<GppC3voltSelect value="3.3Volts" value_list="['3.3Volts', '1.8Volts']" label="GPP_C3 Individual Voltage Select" help_text="This setting controls the VCCIO voltage for the GPP_C3 GPIO pin." key="DescriptorPlugin:PchStraps:PCH_Strap_GPCOM4_gpio_sstrap_vccio_pad_gppc_c3"/>
<GppC4voltSelect value="3.3Volts" value_list="['3.3Volts', '1.8Volts']" label="GPP_C4 Individual Voltage Select" help_text="This setting controls the VCCIO voltage for the GPP_C4 GPIO pin." key="DescriptorPlugin:PchStraps:PCH_Strap_GPCOM4_gpio_sstrap_vccio_pad_gppc_c4"/>
<GppC5voltSelect value="3.3Volts" value_list="['3.3Volts', '1.8Volts']" label="GPP_C5 Individual Voltage Select" help_text="This setting controls the VCCIO voltage for the GPP_C5 GPIO pin." key="DescriptorPlugin:PchStraps:PCH_Strap_GPCOM4_gpio_sstrap_vccio_pad_gppc_c5"/>
<GppC6voltSelect value="3.3Volts" value_list="['3.3Volts', '1.8Volts']" label="GPP_C6 Individual Voltage Select" help_text="This setting controls the VCCIO voltage for the GPP_C6 GPIO pin." key="DescriptorPlugin:PchStraps:PCH_Strap_GPCOM4_gpio_sstrap_vccio_pad_gppc_c6"/>
<GppC7voltSelect value="3.3Volts" value_list="['3.3Volts', '1.8Volts']" label="GPP_C7 Individual Voltage Select" help_text="This setting controls the VCCIO voltage for the GPP_C7 GPIO pin." key="DescriptorPlugin:PchStraps:PCH_Strap_GPCOM4_gpio_sstrap_vccio_pad_gppc_c7"/>
<GppE0voltSelect value="3.3Volts" value_list="['3.3Volts', '1.8Volts']" label="GPP_E0 Individual Voltage Select" help_text="This setting controls the VCCIO voltage for the GPP_E0 GPIO pin." key="DescriptorPlugin:PchStraps:PCH_Strap_GPCOM4_gpio_sstrap_vccio_pad_gppc_e0"/>
<GppE1voltSelect value="3.3Volts" value_list="['3.3Volts', '1.8Volts']" label="GPP_E1 Individual Voltage Select" help_text="This setting controls the VCCIO voltage for the GPP_E1 GPIO pin." key="DescriptorPlugin:PchStraps:PCH_Strap_GPCOM4_gpio_sstrap_vccio_pad_gppc_e1"/>
<GppE2voltSelect value="3.3Volts" value_list="['3.3Volts', '1.8Volts']" label="GPP_E2 Individual Voltage Select" help_text="This setting controls the VCCIO voltage for the GPP_E2 GPIO pin." key="DescriptorPlugin:PchStraps:PCH_Strap_GPCOM4_gpio_sstrap_vccio_pad_gppc_e2"/>
<GppE3voltSelect value="3.3Volts" value_list="['3.3Volts', '1.8Volts']" label="GPP_E3 Individual Voltage Select" help_text="This setting controls the VCCIO voltage for the GPP_E3 GPIO pin." key="DescriptorPlugin:PchStraps:PCH_Strap_GPCOM4_gpio_sstrap_vccio_pad_gppc_e3"/>
<GppE4voltSelect value="3.3Volts" value_list="['3.3Volts', '1.8Volts']" label="GPP_E4 Individual Voltage Select" help_text="This setting controls the VCCIO voltage for the GPP_E4 GPIO pin." key="DescriptorPlugin:PchStraps:PCH_Strap_GPCOM4_gpio_sstrap_vccio_pad_gppc_e4"/>
<GppE5voltSelect value="3.3Volts" value_list="['3.3Volts', '1.8Volts']" label="GPP_E5 Individual Voltage Select" help_text="This setting controls the VCCIO voltage for the GPP_E5 GPIO pin." key="DescriptorPlugin:PchStraps:PCH_Strap_GPCOM4_gpio_sstrap_vccio_pad_gppc_e5"/>
<GppE6voltSelect value="3.3Volts" value_list="['3.3Volts', '1.8Volts']" label="GPP_E6 Individual Voltage Select" help_text="This setting controls the VCCIO voltage for the GPP_E6 GPIO pin." key="DescriptorPlugin:PchStraps:PCH_Strap_GPCOM4_gpio_sstrap_vccio_pad_gppc_e6"/>
<GppE7voltSelect value="3.3Volts" value_list="['3.3Volts', '1.8Volts']" label="GPP_E7 Individual Voltage Select" help_text="This setting controls the VCCIO voltage for the GPP_E7 GPIO pin." key="DescriptorPlugin:PchStraps:PCH_Strap_GPCOM4_gpio_sstrap_vccio_pad_gppc_e7"/>
<GppE8voltSelect value="3.3Volts" value_list="['3.3Volts', '1.8Volts']" label="GPP_E8 Individual Voltage Select" help_text="This setting controls the VCCIO voltage for the GPP_E8 GPIO pin." key="DescriptorPlugin:PchStraps:PCH_Strap_GPCOM4_gpio_sstrap_vccio_pad_gppc_e8"/>
<GppE9voltSelect value="3.3Volts" value_list="['3.3Volts', '1.8Volts']" label="GPP_E9 Individual Voltage Select" help_text="This setting controls the VCCIO voltage for the GPP_E9 GPIO pin." key="DescriptorPlugin:PchStraps:PCH_Strap_GPCOM4_gpio_sstrap_vccio_pad_gppc_e9"/>
<GppE10voltSelect value="3.3Volts" value_list="['3.3Volts', '1.8Volts']" label="GPP_E10 Individual Voltage Select" help_text="This setting controls the VCCIO voltage for the GPP_E10 GPIO pin." key="DescriptorPlugin:PchStraps:PCH_Strap_GPCOM4_gpio_sstrap_vccio_pad_gppc_e10"/>
<GppE11voltSelect value="3.3Volts" value_list="['3.3Volts', '1.8Volts']" label="GPP_E11 Individual Voltage Select" help_text="This setting controls the VCCIO voltage for the GPP_E11 GPIO pin." key="DescriptorPlugin:PchStraps:PCH_Strap_GPCOM4_gpio_sstrap_vccio_pad_gppc_e11"/>
<GppE12voltSelect value="3.3Volts" value_list="['3.3Volts', '1.8Volts']" label="GPP_E12 Individual Voltage Select" help_text="This setting controls the VCCIO voltage for the GPP_E12 GPIO pin." key="DescriptorPlugin:PchStraps:PCH_Strap_GPCOM4_gpio_sstrap_vccio_pad_gppc_e12"/>
<GppE13voltSelect value="3.3Volts" value_list="['3.3Volts', '1.8Volts']" label="GPP_E13 Individual Voltage Select" help_text="This setting controls the VCCIO voltage for the GPP_E13 GPIO pin." key="DescriptorPlugin:PchStraps:PCH_Strap_GPCOM4_gpio_sstrap_vccio_pad_gppc_e13"/>
<GppE14voltSelect value="3.3Volts" value_list="['3.3Volts', '1.8Volts']" label="GPP_E14 Individual Voltage Select" help_text="This setting controls the VCCIO voltage for the GPP_E14 GPIO pin." key="DescriptorPlugin:PchStraps:PCH_Strap_GPCOM4_gpio_sstrap_vccio_pad_gppc_e14"/>
<GppE15voltSelect value="3.3Volts" value_list="['3.3Volts', '1.8Volts']" label="GPP_E15 Individual Voltage Select" help_text="This setting controls the VCCIO voltage for the GPP_E15 GPIO pin." key="DescriptorPlugin:PchStraps:PCH_Strap_GPCOM4_gpio_sstrap_vccio_pad_gppc_e15"/>
<GppE16voltSelect value="3.3Volts" value_list="['3.3Volts', '1.8Volts']" label="GPP_E16 Individual Voltage Select" help_text="This setting controls the VCCIO voltage for the GPP_E16 GPIO pin." key="DescriptorPlugin:PchStraps:PCH_Strap_GPCOM4_gpio_sstrap_vccio_pad_gppc_e16"/>
<GppE17voltSelect value="3.3Volts" value_list="['3.3Volts', '1.8Volts']" label="GPP_E17 Individual Voltage Select" help_text="This setting controls the VCCIO voltage for the GPP_E17 GPIO pin." key="DescriptorPlugin:PchStraps:PCH_Strap_GPCOM4_gpio_sstrap_vccio_pad_gppc_e17"/>
<GppE18voltSelect value="3.3Volts" value_list="['3.3Volts', '1.8Volts']" label="GPP_E18 Individual Voltage Select" help_text="This setting controls the VCCIO voltage for the GPP_E18 GPIO pin." key="DescriptorPlugin:PchStraps:PCH_Strap_GPCOM4_gpio_sstrap_vccio_pad_gppc_e18"/>
<GppE19voltSelect value="3.3Volts" value_list="['3.3Volts', '1.8Volts']" label="GPP_E19 Individual Voltage Select" help_text="This setting controls the VCCIO voltage for the GPP_E19 GPIO pin." key="DescriptorPlugin:PchStraps:PCH_Strap_GPCOM4_gpio_sstrap_vccio_pad_gppc_e19"/>
<GppE20voltSelect value="3.3Volts" value_list="['3.3Volts', '1.8Volts']" label="GPP_E20 Individual Voltage Select" help_text="This setting controls the VCCIO voltage for the GPP_E20 GPIO pin." key="DescriptorPlugin:PchStraps:PCH_Strap_GPCOM4_gpio_sstrap_vccio_pad_gppc_e20"/>
<GppE21voltSelect value="3.3Volts" value_list="['3.3Volts', '1.8Volts']" label="GPP_E21 Individual Voltage Select" help_text="This setting controls the VCCIO voltage for the GPP_E21 GPIO pin." key="DescriptorPlugin:PchStraps:PCH_Strap_GPCOM4_gpio_sstrap_vccio_pad_gppc_e21"/>
<GppE22voltSelect value="3.3Volts" value_list="['3.3Volts', '1.8Volts']" label="GPP_E22 Individual Voltage Select" help_text="This setting controls the VCCIO voltage for the GPP_E22 GPIO pin." key="DescriptorPlugin:PchStraps:PCH_Strap_GPCOM4_gpio_sstrap_vccio_pad_gppc_e22"/>
<GppE23voltSelect value="3.3Volts" value_list="['3.3Volts', '1.8Volts']" label="GPP_E23 Individual Voltage Select" help_text="This setting controls the VCCIO voltage for the GPP_E23 GPIO pin." key="DescriptorPlugin:PchStraps:PCH_Strap_GPCOM4_gpio_sstrap_vccio_pad_gppc_e23"/>
<GppF0voltSelect value="1.8Volts" value_list="['3.3Volts', '1.8Volts']" label="GPP_F0 Individual Voltage Select" help_text="This setting controls the VCCIO voltage for the GPP_F0 GPIO pin." key="DescriptorPlugin:PchStraps:PCH_Strap_GPCOM4_gpio_sstrap_vccio_pad_gppc_f0"/>
<GppF1voltSelect value="1.8Volts" value_list="['3.3Volts', '1.8Volts']" label="GPP_F1 Individual Voltage Select" help_text="This setting controls the VCCIO voltage for the GPP_F1 GPIO pin." key="DescriptorPlugin:PchStraps:PCH_Strap_GPCOM4_gpio_sstrap_vccio_pad_gppc_f1"/>
<GppF2voltSelect value="1.8Volts" value_list="['3.3Volts', '1.8Volts']" label="GPP_F2 Individual Voltage Select" help_text="This setting controls the VCCIO voltage for the GPP_F2 GPIO pin." key="DescriptorPlugin:PchStraps:PCH_Strap_GPCOM4_gpio_sstrap_vccio_pad_gppc_f2"/>
<GppF3voltSelect value="1.8Volts" value_list="['3.3Volts', '1.8Volts']" label="GPP_F3 Individual Voltage Select" help_text="This setting controls the VCCIO voltage for the GPP_F3 GPIO pin." key="DescriptorPlugin:PchStraps:PCH_Strap_GPCOM4_gpio_sstrap_vccio_pad_gppc_f3"/>
<GppF4voltSelect value="1.8Volts" value_list="['3.3Volts', '1.8Volts']" label="GPP_F4 Individual Voltage Select" help_text="This setting controls the VCCIO voltage for the GPP_F4 GPIO pin." key="DescriptorPlugin:PchStraps:PCH_Strap_GPCOM4_gpio_sstrap_vccio_pad_gppc_f4"/>
<GppF5voltSelect value="1.8Volts" value_list="['3.3Volts', '1.8Volts']" label="GPP_F5 Individual Voltage Select" help_text="This setting controls the VCCIO voltage for the GPP_F5 GPIO pin." key="DescriptorPlugin:PchStraps:PCH_Strap_GPCOM4_gpio_sstrap_vccio_pad_gppc_f5"/>
<GppF6voltSelect value="1.8Volts" value_list="['3.3Volts', '1.8Volts']" label="GPP_F6 Individual Voltage Select" help_text="This setting controls the VCCIO voltage for the GPP_F6 GPIO pin." key="DescriptorPlugin:PchStraps:PCH_Strap_GPCOM4_gpio_sstrap_vccio_pad_gppc_f6"/>
<GppF7voltSelect value="1.8Volts" value_list="['3.3Volts', '1.8Volts']" label="GPP_F7 Individual Voltage Select" help_text="This setting controls the VCCIO voltage for the GPP_F7 GPIO pin." key="DescriptorPlugin:PchStraps:PCH_Strap_GPCOM4_gpio_sstrap_vccio_pad_gppc_f7"/>
<GppF9voltSelect value="1.8Volts" value_list="['3.3Volts', '1.8Volts']" label="GPP_F9 Individual Voltage Select" help_text="This setting controls the VCCIO voltage for the GPP_F9 GPIO pin." key="DescriptorPlugin:PchStraps:PCH_Strap_GPCOM4_gpio_sstrap_vccio_pad_gppc_f9"/>
<GppF10voltSelect value="1.8Volts" value_list="['3.3Volts', '1.8Volts']" label="GPP_F10 Individual Voltage Select" help_text="This setting controls the VCCIO voltage for the GPP_F10 GPIO pin." key="DescriptorPlugin:PchStraps:PCH_Strap_GPCOM4_gpio_sstrap_vccio_pad_gppc_f10"/>
<GppF11voltSelect value="1.8Volts" value_list="['3.3Volts', '1.8Volts']" label="GPP_F11 Individual Voltage Select" help_text="This setting controls the VCCIO voltage for the GPP_F11 GPIO pin." key="DescriptorPlugin:PchStraps:PCH_Strap_GPCOM4_gpio_sstrap_vccio_pad_gppc_f11"/>
<GppF12voltSelect value="1.8Volts" value_list="['3.3Volts', '1.8Volts']" label="GPP_F12 Individual Voltage Select" help_text="This setting controls the VCCIO voltage for the GPP_F12 GPIO pin." key="DescriptorPlugin:PchStraps:PCH_Strap_GPCOM4_gpio_sstrap_vccio_pad_gppc_f12"/>
<GppF13voltSelect value="1.8Volts" value_list="['3.3Volts', '1.8Volts']" label="GPP_F13 Individual Voltage Select" help_text="This setting controls the VCCIO voltage for the GPP_F13 GPIO pin." key="DescriptorPlugin:PchStraps:PCH_Strap_GPCOM4_gpio_sstrap_vccio_pad_gppc_f13"/>
<GppF14voltSelect value="1.8Volts" value_list="['3.3Volts', '1.8Volts']" label="GPP_F14 Individual Voltage Select" help_text="This setting controls the VCCIO voltage for the GPP_F14 GPIO pin." key="DescriptorPlugin:PchStraps:PCH_Strap_GPCOM4_gpio_sstrap_vccio_pad_gppc_f14"/>
<GppF15voltSelect value="1.8Volts" value_list="['3.3Volts', '1.8Volts']" label="GPP_F15 Individual Voltage Select" help_text="This setting controls the VCCIO voltage for the GPP_F15 GPIO pin." key="DescriptorPlugin:PchStraps:PCH_Strap_GPCOM4_gpio_sstrap_vccio_pad_gppc_f15"/>
<GppF16voltSelect value="1.8Volts" value_list="['3.3Volts', '1.8Volts']" label="GPP_F16 Individual Voltage Select" help_text="This setting controls the VCCIO voltage for the GPP_F16 GPIO pin." key="DescriptorPlugin:PchStraps:PCH_Strap_GPCOM4_gpio_sstrap_vccio_pad_gppc_f16"/>
<GppF17voltSelect value="1.8Volts" value_list="['3.3Volts', '1.8Volts']" label="GPP_F17 Individual Voltage Select" help_text="This setting controls the VCCIO voltage for the GPP_F17 GPIO pin." key="DescriptorPlugin:PchStraps:PCH_Strap_GPCOM4_gpio_sstrap_vccio_pad_gppc_f17"/>
<GppF18voltSelect value="1.8Volts" value_list="['3.3Volts', '1.8Volts']" label="GPP_F18 Individual Voltage Select" help_text="This setting controls the VCCIO voltage for the GPP_F18 GPIO pin." key="DescriptorPlugin:PchStraps:PCH_Strap_GPCOM4_gpio_sstrap_vccio_pad_gppc_f18"/>
<GppF19voltSelect value="1.8Volts" value_list="['3.3Volts', '1.8Volts']" label="GPP_F19 Individual Voltage Select" help_text="This setting controls the VCCIO voltage for the GPP_F19 GPIO pin." key="DescriptorPlugin:PchStraps:PCH_Strap_GPCOM4_gpio_sstrap_vccio_pad_gppc_f19"/>
<GppF20voltSelect value="1.8Volts" value_list="['3.3Volts', '1.8Volts']" label="GPP_F20 Individual Voltage Select" help_text="This setting controls the VCCIO voltage for the GPP_F20 GPIO pin." key="DescriptorPlugin:PchStraps:PCH_Strap_GPCOM4_gpio_sstrap_vccio_pad_gppc_f20"/>
<GppF21voltSelect value="1.8Volts" value_list="['3.3Volts', '1.8Volts']" label="GPP_F21 Individual Voltage Select" help_text="This setting controls the VCCIO voltage for the GPP_F21 GPIO pin." key="DescriptorPlugin:PchStraps:PCH_Strap_GPCOM4_gpio_sstrap_vccio_pad_gppc_f21"/>
<GppF22voltSelect value="1.8Volts" value_list="['3.3Volts', '1.8Volts']" label="GPP_F22 Individual Voltage Select" help_text="This setting controls the VCCIO voltage for the GPP_F22 GPIO pin." key="DescriptorPlugin:PchStraps:PCH_Strap_GPCOM4_gpio_sstrap_vccio_pad_gppc_f22"/>
<GppF23voltSelect value="1.8Volts" value_list="['3.3Volts', '1.8Volts']" label="GPP_F23 Individual Voltage Select" help_text="This setting controls the VCCIO voltage for the GPP_F23 GPIO pin." key="DescriptorPlugin:PchStraps:PCH_Strap_GPCOM4_gpio_sstrap_vccio_pad_gppc_f23"/>
<GppD0voltSelect value="3.3Volts" value_list="['3.3Volts', '1.8Volts']" label="GPP_D0 Individual Voltage Select" help_text="This setting controls the VCCIO voltage for the GPP_D0 GPIO pin." key="DescriptorPlugin:PchStraps:PCH_Strap_GPCOM1_gpio_sstrap_vccio_pad_gppc_d0"/>
<GppD1voltSelect value="3.3Volts" value_list="['3.3Volts', '1.8Volts']" label="GPP_D1 Individual Voltage Select" help_text="This setting controls the VCCIO voltage for the GPP_D1 GPIO pin." key="DescriptorPlugin:PchStraps:PCH_Strap_GPCOM1_gpio_sstrap_vccio_pad_gppc_d1"/>
<GppD2voltSelect value="3.3Volts" value_list="['3.3Volts', '1.8Volts']" label="GPP_D2 Individual Voltage Select" help_text="This setting controls the VCCIO voltage for the GPP_D2 GPIO pin." key="DescriptorPlugin:PchStraps:PCH_Strap_GPCOM1_gpio_sstrap_vccio_pad_gppc_d2"/>
<GppD3voltSelect value="3.3Volts" value_list="['3.3Volts', '1.8Volts']" label="GPP_D3 Individual Voltage Select" help_text="This setting controls the VCCIO voltage for the GPP_D3 GPIO pin." key="DescriptorPlugin:PchStraps:PCH_Strap_GPCOM1_gpio_sstrap_vccio_pad_gppc_d3"/>
<GppD4voltSelect value="3.3Volts" value_list="['3.3Volts', '1.8Volts']" label="GPP_D4 Individual Voltage Select" help_text="This setting controls the VCCIO voltage for the GPP_D4 GPIO pin." key="DescriptorPlugin:PchStraps:PCH_Strap_GPCOM1_gpio_sstrap_vccio_pad_gppc_d4"/>
<GppD5voltSelect value="3.3Volts" value_list="['3.3Volts', '1.8Volts']" label="GPP_D5 Individual Voltage Select" help_text="This setting controls the VCCIO voltage for the GPP_D5 GPIO pin." key="DescriptorPlugin:PchStraps:PCH_Strap_GPCOM1_gpio_sstrap_vccio_pad_gppc_d5"/>
<GppD6voltSelect value="3.3Volts" value_list="['3.3Volts', '1.8Volts']" label="GPP_D6 Individual Voltage Select" help_text="This setting controls the VCCIO voltage for the GPP_D6 GPIO pin." key="DescriptorPlugin:PchStraps:PCH_Strap_GPCOM1_gpio_sstrap_vccio_pad_gppc_d6"/>
<GppD7voltSelect value="3.3Volts" value_list="['3.3Volts', '1.8Volts']" label="GPP_D7 Individual Voltage Select" help_text="This setting controls the VCCIO voltage for the GPP_D7 GPIO pin." key="DescriptorPlugin:PchStraps:PCH_Strap_GPCOM1_gpio_sstrap_vccio_pad_gppc_d7"/>
<GppD8voltSelect value="3.3Volts" value_list="['3.3Volts', '1.8Volts']" label="GPP_D8 Individual Voltage Select" help_text="This setting controls the VCCIO voltage for the GPP_D8 GPIO pin." key="DescriptorPlugin:PchStraps:PCH_Strap_GPCOM1_gpio_sstrap_vccio_pad_gppc_d8"/>
<GppD9voltSelect value="3.3Volts" value_list="['3.3Volts', '1.8Volts']" label="GPP_D9 Individual Voltage Select" help_text="This setting controls the VCCIO voltage for the GPP_D9 GPIO pin." key="DescriptorPlugin:PchStraps:PCH_Strap_GPCOM1_gpio_sstrap_vccio_pad_gppc_d9"/>
<GppD10voltSelect value="3.3Volts" value_list="['3.3Volts', '1.8Volts']" label="GPP_D10 Individual Voltage Select" help_text="This setting controls the VCCIO voltage for the GPP_D10 GPIO pin." key="DescriptorPlugin:PchStraps:PCH_Strap_GPCOM1_gpio_sstrap_vccio_pad_gppc_d10"/>
<GppD11voltSelect value="3.3Volts" value_list="['3.3Volts', '1.8Volts']" label="GPP_D11 Individual Voltage Select" help_text="This setting controls the VCCIO voltage for the GPP_D11 GPIO pin." key="DescriptorPlugin:PchStraps:PCH_Strap_GPCOM1_gpio_sstrap_vccio_pad_gppc_d11"/>
<GppD12voltSelect value="3.3Volts" value_list="['3.3Volts', '1.8Volts']" label="GPP_D12 Individual Voltage Select" help_text="This setting controls the VCCIO voltage for the GPP_D12 GPIO pin." key="DescriptorPlugin:PchStraps:PCH_Strap_GPCOM1_gpio_sstrap_vccio_pad_gppc_d12"/>
<GppD13voltSelect value="3.3Volts" value_list="['3.3Volts', '1.8Volts']" label="GPP_D13 Individual Voltage Select" help_text="This setting controls the VCCIO voltage for the GPP_D13 GPIO pin." key="DescriptorPlugin:PchStraps:PCH_Strap_GPCOM1_gpio_sstrap_vccio_pad_gppc_d13"/>
<GppD14voltSelect value="3.3Volts" value_list="['3.3Volts', '1.8Volts']" label="GPP_D14 Individual Voltage Select" help_text="This setting controls the VCCIO voltage for the GPP_D14 GPIO pin." key="DescriptorPlugin:PchStraps:PCH_Strap_GPCOM1_gpio_sstrap_vccio_pad_gppc_d14"/>
<GppD15voltSelect value="3.3Volts" value_list="['3.3Volts', '1.8Volts']" label="GPP_D15 Individual Voltage Select" help_text="This setting controls the VCCIO voltage for the GPP_D15 GPIO pin." key="DescriptorPlugin:PchStraps:PCH_Strap_GPCOM1_gpio_sstrap_vccio_pad_gppc_d15"/>
<GppD16voltSelect value="3.3Volts" value_list="['3.3Volts', '1.8Volts']" label="GPP_D16 Individual Voltage Select" help_text="This setting controls the VCCIO voltage for the GPP_D16 GPIO pin." key="DescriptorPlugin:PchStraps:PCH_Strap_GPCOM1_gpio_sstrap_vccio_pad_gppc_d16"/>
<GppD17voltSelect value="3.3Volts" value_list="['3.3Volts', '1.8Volts']" label="GPP_D17 Individual Voltage Select" help_text="This setting controls the VCCIO voltage for the GPP_D17 GPIO pin." key="DescriptorPlugin:PchStraps:PCH_Strap_GPCOM1_gpio_sstrap_vccio_pad_gppc_d17"/>
<GppD18voltSelect value="3.3Volts" value_list="['3.3Volts', '1.8Volts']" label="GPP_D18 Individual Voltage Select" help_text="This setting controls the VCCIO voltage for the GPP_D18 GPIO pin." key="DescriptorPlugin:PchStraps:PCH_Strap_GPCOM1_gpio_sstrap_vccio_pad_gppc_d18"/>
<GppD19voltSelect value="3.3Volts" value_list="['3.3Volts', '1.8Volts']" label="GPP_D19 Individual Voltage Select" help_text="This setting controls the VCCIO voltage for the GPP_D19 GPIO pin." key="DescriptorPlugin:PchStraps:PCH_Strap_GPCOM1_gpio_sstrap_vccio_pad_gppc_d19"/>
<GppH0voltSelect value="3.3Volts" value_list="['3.3Volts', '1.8Volts']" label="GPP_H0 Individual Voltage Select" help_text="This setting controls the VCCIO voltage for the GPP_H0 GPIO pin." key="DescriptorPlugin:PchStraps:PCH_Strap_GPCOM1_gpio_sstrap_vccio_pad_gppc_h0"/>
<GppH1voltSelect value="3.3Volts" value_list="['3.3Volts', '1.8Volts']" label="GPP_H1 Individual Voltage Select" help_text="This setting controls the VCCIO voltage for the GPP_H1 GPIO pin." key="DescriptorPlugin:PchStraps:PCH_Strap_GPCOM1_gpio_sstrap_vccio_pad_gppc_h1"/>
<GppH2voltSelect value="3.3Volts" value_list="['3.3Volts', '1.8Volts']" label="GPP_H2 Individual Voltage Select" help_text="This setting controls the VCCIO voltage for the GPP_H2 GPIO pin." key="DescriptorPlugin:PchStraps:PCH_Strap_GPCOM1_gpio_sstrap_vccio_pad_gppc_h2"/>
<GppH3voltSelect value="3.3Volts" value_list="['3.3Volts', '1.8Volts']" label="GPP_H3 Individual Voltage Select" help_text="This setting controls the VCCIO voltage for the GPP_H3 GPIO pin." key="DescriptorPlugin:PchStraps:PCH_Strap_GPCOM1_gpio_sstrap_vccio_pad_gppc_h3"/>
<GppH4voltSelect value="3.3Volts" value_list="['3.3Volts', '1.8Volts']" label="GPP_H4 Individual Voltage Select" help_text="This setting controls the VCCIO voltage for the GPP_H4 GPIO pin." key="DescriptorPlugin:PchStraps:PCH_Strap_GPCOM1_gpio_sstrap_vccio_pad_gppc_h4"/>
<GppH5voltSelect value="3.3Volts" value_list="['3.3Volts', '1.8Volts']" label="GPP_H5 Individual Voltage Select" help_text="This setting controls the VCCIO voltage for the GPP_H5 GPIO pin." key="DescriptorPlugin:PchStraps:PCH_Strap_GPCOM1_gpio_sstrap_vccio_pad_gppc_h5"/>
<GppH6voltSelect value="3.3Volts" value_list="['3.3Volts', '1.8Volts']" label="GPP_H6 Individual Voltage Select" help_text="This setting controls the VCCIO voltage for the GPP_H6 GPIO pin." key="DescriptorPlugin:PchStraps:PCH_Strap_GPCOM1_gpio_sstrap_vccio_pad_gppc_h6"/>
<GppH7voltSelect value="3.3Volts" value_list="['3.3Volts', '1.8Volts']" label="GPP_H7 Individual Voltage Select" help_text="This setting controls the VCCIO voltage for the GPP_H7 GPIO pin." key="DescriptorPlugin:PchStraps:PCH_Strap_GPCOM1_gpio_sstrap_vccio_pad_gppc_h7"/>
<GppH8voltSelect value="3.3Volts" value_list="['3.3Volts', '1.8Volts']" label="GPP_H8 Individual Voltage Select" help_text="This setting controls the VCCIO voltage for the GPP_H8 GPIO pin." key="DescriptorPlugin:PchStraps:PCH_Strap_GPCOM1_gpio_sstrap_vccio_pad_gppc_h8"/>
<GppH9voltSelect value="3.3Volts" value_list="['3.3Volts', '1.8Volts']" label="GPP_H9 Individual Voltage Select" help_text="This setting controls the VCCIO voltage for the GPP_H9 GPIO pin." key="DescriptorPlugin:PchStraps:PCH_Strap_GPCOM1_gpio_sstrap_vccio_pad_gppc_h9"/>
<GppH10voltSelect value="3.3Volts" value_list="['3.3Volts', '1.8Volts']" label="GPP_H10 Individual Voltage Select" help_text="This setting controls the VCCIO voltage for the GPP_H10 GPIO pin." key="DescriptorPlugin:PchStraps:PCH_Strap_GPCOM1_gpio_sstrap_vccio_pad_gppc_h10"/>
<GppH11voltSelect value="3.3Volts" value_list="['3.3Volts', '1.8Volts']" label="GPP_H11 Individual Voltage Select" help_text="This setting controls the VCCIO voltage for the GPP_H11 GPIO pin." key="DescriptorPlugin:PchStraps:PCH_Strap_GPCOM1_gpio_sstrap_vccio_pad_gppc_h11"/>
<GppH12voltSelect value="3.3Volts" value_list="['3.3Volts', '1.8Volts']" label="GPP_H12 Individual Voltage Select" help_text="This setting controls the VCCIO voltage for the GPP_H12 GPIO pin." key="DescriptorPlugin:PchStraps:PCH_Strap_GPCOM1_gpio_sstrap_vccio_pad_gppc_h12"/>
<GppH13voltSelect value="3.3Volts" value_list="['3.3Volts', '1.8Volts']" label="GPP_H13 Individual Voltage Select" help_text="This setting controls the VCCIO voltage for the GPP_H13 GPIO pin." key="DescriptorPlugin:PchStraps:PCH_Strap_GPCOM1_gpio_sstrap_vccio_pad_gppc_h13"/>
<GppH15voltSelect value="3.3Volts" value_list="['3.3Volts', '1.8Volts']" label="GPP_H15 Individual Voltage Select" help_text="This setting controls the VCCIO voltage for the GPP_H15 GPIO pin." key="DescriptorPlugin:PchStraps:PCH_Strap_GPCOM1_gpio_sstrap_vccio_pad_gppc_h15"/>
<GppH17voltSelect value="3.3Volts" value_list="['3.3Volts', '1.8Volts']" label="GPP_H17 Individual Voltage Select" help_text="This setting controls the VCCIO voltage for the GPP_H17 GPIO pin." key="DescriptorPlugin:PchStraps:PCH_Strap_GPCOM1_gpio_sstrap_vccio_pad_gppc_h17"/>
<GppH18voltSelect value="3.3Volts" value_list="['3.3Volts', '1.8Volts']" label="GPP_H18 Individual Voltage Select" help_text="This setting controls the VCCIO voltage for the GPP_H18 GPIO pin." key="DescriptorPlugin:PchStraps:PCH_Strap_GPCOM1_gpio_sstrap_vccio_pad_gppc_h18"/>
<GppH19voltSelect value="3.3Volts" value_list="['3.3Volts', '1.8Volts']" label="GPP_H19 Individual Voltage Select" help_text="This setting controls the VCCIO voltage for the GPP_H19 GPIO pin." key="DescriptorPlugin:PchStraps:PCH_Strap_GPCOM1_gpio_sstrap_vccio_pad_gppc_h19"/>
<GppH20voltSelect value="3.3Volts" value_list="['3.3Volts', '1.8Volts']" label="GPP_H20 Individual Voltage Select" help_text="This setting controls the VCCIO voltage for the GPP_H20 GPIO pin." key="DescriptorPlugin:PchStraps:PCH_Strap_GPCOM1_gpio_sstrap_vccio_pad_gppc_h20"/>
<GppH21voltSelect value="3.3Volts" value_list="['3.3Volts', '1.8Volts']" label="GPP_H21 Individual Voltage Select" help_text="This setting controls the VCCIO voltage for the GPP_H21 GPIO pin." key="DescriptorPlugin:PchStraps:PCH_Strap_GPCOM1_gpio_sstrap_vccio_pad_gppc_h21"/>
<GppH22voltSelect value="3.3Volts" value_list="['3.3Volts', '1.8Volts']" label="GPP_H22 Individual Voltage Select" help_text="This setting controls the VCCIO voltage for the GPP_H22 GPIO pin." key="DescriptorPlugin:PchStraps:PCH_Strap_GPCOM1_gpio_sstrap_vccio_pad_gppc_h22"/>
<GppH23voltSelect value="3.3Volts" value_list="['3.3Volts', '1.8Volts']" label="GPP_H23 Individual Voltage Select" help_text="This setting controls the VCCIO voltage for the GPP_H23 GPIO pin." key="DescriptorPlugin:PchStraps:PCH_Strap_GPCOM1_gpio_sstrap_vccio_pad_gppc_h23"/>
<GppA0voltSelect value="1.8Volts" value_list="['3.3Volts', '1.8Volts']" label="GPP_A0 Individual Voltage Select" help_text="This setting controls the VCCIO voltage for the GPP_A0 GPIO pin." key="DescriptorPlugin:PchStraps:PCH_Strap_GPCOM0_gpio_sstrap_vccio_pad_gppc_a0"/>
<GppA1voltSelect value="1.8Volts" value_list="['3.3Volts', '1.8Volts']" label="GPP_A1 Individual Voltage Select" help_text="This setting controls the VCCIO voltage for the GPP_A1 GPIO pin." key="DescriptorPlugin:PchStraps:PCH_Strap_GPCOM0_gpio_sstrap_vccio_pad_gppc_a1"/>
<GppA2voltSelect value="1.8Volts" value_list="['3.3Volts', '1.8Volts']" label="GPP_A2 Individual Voltage Select" help_text="This setting controls the VCCIO voltage for the GPP_A2 GPIO pin." key="DescriptorPlugin:PchStraps:PCH_Strap_GPCOM0_gpio_sstrap_vccio_pad_gppc_a2"/>
<GppA3voltSelect value="1.8Volts" value_list="['3.3Volts', '1.8Volts']" label="GPP_A3 Individual Voltage Select" help_text="This setting controls the VCCIO voltage for the GPP_A3 GPIO pin." key="DescriptorPlugin:PchStraps:PCH_Strap_GPCOM0_gpio_sstrap_vccio_pad_gppc_a3"/>
<GppA4voltSelect value="1.8Volts" value_list="['3.3Volts', '1.8Volts']" label="GPP_A4 Individual Voltage Select" help_text="This setting controls the VCCIO voltage for the GPP_A4 GPIO pin." key="DescriptorPlugin:PchStraps:PCH_Strap_GPCOM0_gpio_sstrap_vccio_pad_gppc_a4"/>
<GppA5voltSelect value="1.8Volts" value_list="['3.3Volts', '1.8Volts']" label="GPP_A5 Individual Voltage Select" help_text="This setting controls the VCCIO voltage for the GPP_A5 GPIO pin." key="DescriptorPlugin:PchStraps:PCH_Strap_GPCOM0_gpio_sstrap_vccio_pad_gppc_a5"/>
<GppA6voltSelect value="1.8Volts" value_list="['3.3Volts', '1.8Volts']" label="GPP_A6 Individual Voltage Select" help_text="This setting controls the VCCIO voltage for the GPP_A6 GPIO pin." key="DescriptorPlugin:PchStraps:PCH_Strap_GPCOM0_gpio_sstrap_vccio_pad_gppc_a6"/>
<GppA7voltSelect value="1.8Volts" value_list="['3.3Volts', '1.8Volts']" label="GPP_A7 Individual Voltage Select" help_text="This setting controls the VCCIO voltage for the GPP_A7 GPIO pin." key="DescriptorPlugin:PchStraps:PCH_Strap_GPCOM0_gpio_sstrap_vccio_pad_gppc_a7"/>
<GppA8voltSelect value="1.8Volts" value_list="['3.3Volts', '1.8Volts']" label="GPP_A8 Individual Voltage Select" help_text="This setting controls the VCCIO voltage for the GPP_A8 GPIO pin." key="DescriptorPlugin:PchStraps:PCH_Strap_GPCOM0_gpio_sstrap_vccio_pad_gppc_a8"/>
<GppA9voltSelect value="1.8Volts" value_list="['3.3Volts', '1.8Volts']" label="GPP_A9 Individual Voltage Select" help_text="This setting controls the VCCIO voltage for the GPP_A9 GPIO pin." key="DescriptorPlugin:PchStraps:PCH_Strap_GPCOM0_gpio_sstrap_vccio_pad_gppc_a9"/>
<GppA10voltSelect value="1.8Volts" value_list="['3.3Volts', '1.8Volts']" label="GPP_A10 Individual Voltage Select" help_text="This setting controls the VCCIO voltage for the GPP_A10 GPIO pin." key="DescriptorPlugin:PchStraps:PCH_Strap_GPCOM0_gpio_sstrap_vccio_pad_gppc_a10"/>
<GppA11voltSelect value="1.8Volts" value_list="['3.3Volts', '1.8Volts']" label="GPP_A11 Individual Voltage Select" help_text="This setting controls the VCCIO voltage for the GPP_A11 GPIO pin." key="DescriptorPlugin:PchStraps:PCH_Strap_GPCOM0_gpio_sstrap_vccio_pad_gppc_a11"/>
<GppA12voltSelect value="1.8Volts" value_list="['3.3Volts', '1.8Volts']" label="GPP_A12 Individual Voltage Select" help_text="This setting controls the VCCIO voltage for the GPP_A12 GPIO pin." key="DescriptorPlugin:PchStraps:PCH_Strap_GPCOM0_gpio_sstrap_vccio_pad_gppc_a12"/>
<GppA13voltSelect value="1.8Volts" value_list="['3.3Volts', '1.8Volts']" label="GPP_A13 Individual Voltage Select" help_text="This setting controls the VCCIO voltage for the GPP_A13 GPIO pin." key="DescriptorPlugin:PchStraps:PCH_Strap_GPCOM0_gpio_sstrap_vccio_pad_gppc_a13"/>
<GppA14voltSelect value="1.8Volts" value_list="['3.3Volts', '1.8Volts']" label="GPP_A14 Individual Voltage Select" help_text="This setting controls the VCCIO voltage for the GPP_A14 GPIO pin." key="DescriptorPlugin:PchStraps:PCH_Strap_GPCOM0_gpio_sstrap_vccio_pad_gppc_a14"/>
<GppA15voltSelect value="1.8Volts" value_list="['3.3Volts', '1.8Volts']" label="GPP_A15 Individual Voltage Select" help_text="This setting controls the VCCIO voltage for the GPP_A15 GPIO pin." key="DescriptorPlugin:PchStraps:PCH_Strap_GPCOM0_gpio_sstrap_vccio_pad_gppc_a15"/>
<GppA16voltSelect value="1.8Volts" value_list="['3.3Volts', '1.8Volts']" label="GPP_A16 Individual Voltage Select" help_text="This setting controls the VCCIO voltage for the GPP_A16 GPIO pin." key="DescriptorPlugin:PchStraps:PCH_Strap_GPCOM0_gpio_sstrap_vccio_pad_gppc_a16"/>
<GppA17voltSelect value="1.8Volts" value_list="['3.3Volts', '1.8Volts']" label="GPP_A17 Individual Voltage Select" help_text="This setting controls the VCCIO voltage for the GPP_A17 GPIO pin." key="DescriptorPlugin:PchStraps:PCH_Strap_GPCOM0_gpio_sstrap_vccio_pad_gppc_a17"/>
<GppA18voltSelect value="1.8Volts" value_list="['3.3Volts', '1.8Volts']" label="GPP_A18 Individual Voltage Select" help_text="This setting controls the VCCIO voltage for the GPP_A18 GPIO pin." key="DescriptorPlugin:PchStraps:PCH_Strap_GPCOM0_gpio_sstrap_vccio_pad_gppc_a18"/>
<GppA19voltSelect value="1.8Volts" value_list="['3.3Volts', '1.8Volts']" label="GPP_A19 Individual Voltage Select" help_text="This setting controls the VCCIO voltage for the GPP_A19 GPIO pin." key="DescriptorPlugin:PchStraps:PCH_Strap_GPCOM0_gpio_sstrap_vccio_pad_gppc_a19"/>
<GppA20voltSelect value="1.8Volts" value_list="['3.3Volts', '1.8Volts']" label="GPP_A20 Individual Voltage Select" help_text="This setting controls the VCCIO voltage for the GPP_A20 GPIO pin." key="DescriptorPlugin:PchStraps:PCH_Strap_GPCOM0_gpio_sstrap_vccio_pad_gppc_a20"/>
<GppA21voltSelect value="1.8Volts" value_list="['3.3Volts', '1.8Volts']" label="GPP_A21 Individual Voltage Select" help_text="This setting controls the VCCIO voltage for the GPP_A21 GPIO pin." key="DescriptorPlugin:PchStraps:PCH_Strap_GPCOM0_gpio_sstrap_vccio_pad_gppc_a21"/>
<GppA22voltSelect value="1.8Volts" value_list="['3.3Volts', '1.8Volts']" label="GPP_A22 Individual Voltage Select" help_text="This setting controls the VCCIO voltage for the GPP_A22 GPIO pin." key="DescriptorPlugin:PchStraps:PCH_Strap_GPCOM0_gpio_sstrap_vccio_pad_gppc_a22"/>
<GppA23voltSelect value="1.8Volts" value_list="['3.3Volts', '1.8Volts']" label="GPP_A23 Individual Voltage Select" help_text="This setting controls the VCCIO voltage for the GPP_A23 GPIO pin." key="DescriptorPlugin:PchStraps:PCH_Strap_GPCOM0_gpio_sstrap_vccio_pad_gppc_a23"/>
<GppB0voltSelect value="3.3Volts" value_list="['3.3Volts', '1.8Volts']" label="GPP_B0 Individual Voltage Select" help_text="This setting controls the VCCIO voltage for the GPP_B0 GPIO pin." key="DescriptorPlugin:PchStraps:PCH_Strap_GPCOM0_gpio_sstrap_vccio_pad_gppc_b0"/>
<GppB1voltSelect value="3.3Volts" value_list="['3.3Volts', '1.8Volts']" label="GPP_B1 Individual Voltage Select" help_text="This setting controls the VCCIO voltage for the GPP_B1 GPIO pin." key="DescriptorPlugin:PchStraps:PCH_Strap_GPCOM0_gpio_sstrap_vccio_pad_gppc_b1"/>
<GppB2voltSelect value="3.3Volts" value_list="['3.3Volts', '1.8Volts']" label="GPP_B2 Individual Voltage Select" help_text="This setting controls the VCCIO voltage for the GPP_B2 GPIO pin." key="DescriptorPlugin:PchStraps:PCH_Strap_GPCOM0_gpio_sstrap_vccio_pad_gppc_b2"/>
<GppB3voltSelect value="3.3Volts" value_list="['3.3Volts', '1.8Volts']" label="GPP_B3 Individual Voltage Select" help_text="This setting controls the VCCIO voltage for the GPP_B3 GPIO pin." key="DescriptorPlugin:PchStraps:PCH_Strap_GPCOM0_gpio_sstrap_vccio_pad_gppc_b3"/>
<GppB4voltSelect value="3.3Volts" value_list="['3.3Volts', '1.8Volts']" label="GPP_B4 Individual Voltage Select" help_text="This setting controls the VCCIO voltage for the GPP_B4 GPIO pin." key="DescriptorPlugin:PchStraps:PCH_Strap_GPCOM0_gpio_sstrap_vccio_pad_gppc_b4"/>
<GppB5voltSelect value="3.3Volts" value_list="['3.3Volts', '1.8Volts']" label="GPP_B5 Individual Voltage Select" help_text="This setting controls the VCCIO voltage for the GPP_B5 GPIO pin." key="DescriptorPlugin:PchStraps:PCH_Strap_GPCOM0_gpio_sstrap_vccio_pad_gppc_b5"/>
<GppB6voltSelect value="3.3Volts" value_list="['3.3Volts', '1.8Volts']" label="GPP_B6 Individual Voltage Select" help_text="This setting controls the VCCIO voltage for the GPP_B6 GPIO pin." key="DescriptorPlugin:PchStraps:PCH_Strap_GPCOM0_gpio_sstrap_vccio_pad_gppc_b6"/>
<GppB7voltSelect value="3.3Volts" value_list="['3.3Volts', '1.8Volts']" label="GPP_B7 Individual Voltage Select" help_text="This setting controls the VCCIO voltage for the GPP_B7 GPIO pin." key="DescriptorPlugin:PchStraps:PCH_Strap_GPCOM0_gpio_sstrap_vccio_pad_gppc_b7"/>
<GppB8voltSelect value="3.3Volts" value_list="['3.3Volts', '1.8Volts']" label="GPP_B8 Individual Voltage Select" help_text="This setting controls the VCCIO voltage for the GPP_B8 GPIO pin." key="DescriptorPlugin:PchStraps:PCH_Strap_GPCOM0_gpio_sstrap_vccio_pad_gppc_b8"/>
<GppB11voltSelect value="3.3Volts" value_list="['3.3Volts', '1.8Volts']" label="GPP_B11 Individual Voltage Select" help_text="This setting controls the VCCIO voltage for the GPP_B11 GPIO pin." key="DescriptorPlugin:PchStraps:PCH_Strap_GPCOM0_gpio_sstrap_vccio_pad_gppc_b11"/>
<GppB12voltSelect value="3.3Volts" value_list="['3.3Volts', '1.8Volts']" label="GPP_B12 Individual Voltage Select" help_text="This setting controls the VCCIO voltage for the GPP_B12 GPIO pin." key="DescriptorPlugin:PchStraps:PCH_Strap_GPCOM0_gpio_sstrap_vccio_pad_gppc_b12"/>
<GppB13voltSelect value="3.3Volts" value_list="['3.3Volts', '1.8Volts']" label="GPP_B13 Individual Voltage Select" help_text="This setting controls the VCCIO voltage for the GPP_B13 GPIO pin." key="DescriptorPlugin:PchStraps:PCH_Strap_GPCOM0_gpio_sstrap_vccio_pad_gppc_b13"/>
<GppB14voltSelect value="3.3Volts" value_list="['3.3Volts', '1.8Volts']" label="GPP_B14 Individual Voltage Select" help_text="This setting controls the VCCIO voltage for the GPP_B14 GPIO pin." key="DescriptorPlugin:PchStraps:PCH_Strap_GPCOM0_gpio_sstrap_vccio_pad_gppc_b14"/>
<GppB15voltSelect value="3.3Volts" value_list="['3.3Volts', '1.8Volts']" label="GPP_B15 Individual Voltage Select" help_text="This setting controls the VCCIO voltage for the GPP_B15 GPIO pin." key="DescriptorPlugin:PchStraps:PCH_Strap_GPCOM0_gpio_sstrap_vccio_pad_gppc_b15"/>
<GppB16voltSelect value="3.3Volts" value_list="['3.3Volts', '1.8Volts']" label="GPP_B16 Individual Voltage Select" help_text="This setting controls the VCCIO voltage for the GPP_B16 GPIO pin." key="DescriptorPlugin:PchStraps:PCH_Strap_GPCOM0_gpio_sstrap_vccio_pad_gppc_b16"/>
<GppB17voltSelect value="3.3Volts" value_list="['3.3Volts', '1.8Volts']" label="GPP_B17 Individual Voltage Select" help_text="This setting controls the VCCIO voltage for the GPP_B17 GPIO pin." key="DescriptorPlugin:PchStraps:PCH_Strap_GPCOM0_gpio_sstrap_vccio_pad_gppc_b17"/>
<GppB18voltSelect value="3.3Volts" value_list="['3.3Volts', '1.8Volts']" label="GPP_B18 Individual Voltage Select" help_text="This setting controls the VCCIO voltage for the GPP_B18 GPIO pin." key="DescriptorPlugin:PchStraps:PCH_Strap_GPCOM0_gpio_sstrap_vccio_pad_gppc_b18"/>
<GppB23voltSelect value="3.3Volts" value_list="['3.3Volts', '1.8Volts']" label="GPP_B23 Individual Voltage Select" help_text="This setting controls the VCCIO voltage for the GPP_B23 GPIO pin." key="DescriptorPlugin:PchStraps:PCH_Strap_GPCOM0_gpio_sstrap_vccio_pad_gppc_b23"/>
<GppT2voltSelect value="3.3Volts" value_list="['3.3Volts', '1.8Volts']" label="GPP_T2 Individual Voltage Select" help_text="This setting controls the VCCIO voltage for the GPP_T2 GPIO pin. &lt;br /&gt;Note: GPP_T2 is only available on ADP-P PCH UP3 (not ADP-P PCH UP4)." key="DescriptorPlugin:PchStraps:PCH_Strap_GPCOM0_gpio_sstrap_vccio_pad_gppc_t2"/>
<GppT3voltSelect value="3.3Volts" value_list="['3.3Volts', '1.8Volts']" label="GPP_T3 Individual Voltage Select" help_text="This setting controls the VCCIO voltage for the GPP_T3 GPIO pin. &lt;br /&gt;Note: GPP_T3 is only available on ADP-P PCH UP3 (not ADP-P PCH UP4)." key="DescriptorPlugin:PchStraps:PCH_Strap_GPCOM0_gpio_sstrap_vccio_pad_gppc_t3"/>
</GpioVccioVoltageControl>
<ThunderboltLsxBssb-LsConfiguration label="Thunderbolt LSx/BSSB-LS Configuration">
<TbltLsxBssbLs0Cfg value="TX VCCIO" value_list="['TX VCCIO', 'Legacy VCCIO']" label="Thunderbolt LSx/BSSB-LS 0 VCCIO" help_text="This setting configures Thunderbolt LSx/BSSB-LS 0 VCCIO" key="DescriptorPlugin:PchStraps:PCH_Strap_GPCOM4_gpio_sstrap_vccio_cfg_src0"/>
<TbltLsxBssbLs1Cfg value="TX VCCIO" value_list="['TX VCCIO', 'Legacy VCCIO']" label="Thunderbolt LSx/BSSB-LS 1 VCCIO" help_text="This setting configures ThunderboltTM LSx/BSSB-LS 1 VCCIO" key="DescriptorPlugin:PchStraps:PCH_Strap_GPCOM4_gpio_sstrap_vccio_cfg_src1"/>
<TbltLsxBssbLs2Cfg value="TX VCCIO" value_list="['TX VCCIO', 'Legacy VCCIO']" label="Thunderbolt LSx/BSSB-LS 2 VCCIO" help_text="This setting configures Thunderbolt LSx/BSSB-LS 2 VCCIO" key="DescriptorPlugin:PchStraps:PCH_Strap_GPCOM1_gpio_sstrap_vccio_cfg_src2"/>
<TbltLsxBssbLs3Cfg value="TX VCCIO" value_list="['TX VCCIO', 'Legacy VCCIO']" label="Thunderbolt LSx/BSSB-LS 3 VCCIO" help_text="This setting configures Thunderbolt LSx/BSSB-LS 3 VCCIO" key="DescriptorPlugin:PchStraps:PCH_Strap_GPCOM1_gpio_sstrap_vccio_cfg_src3"/>
</ThunderboltLsxBssb-LsConfiguration>
<CameraPins label="Camera Pins">
<CameraPrivacyGpioPin value="None" value_list="['None', 'GPP_A_0', 'GPP_A_1', 'GPP_A_2', 'GPP_A_3', 'GPP_A_4', 'GPP_A_5', 'GPP_A_6', 'GPP_A_7', 'GPP_A_8', 'GPP_A_9', 'GPP_A_10', 'GPP_A_11', 'GPP_A_13', 'GPP_A_14', 'GPP_A_15', 'GPP_A_16', 'GPP_B_0', 'GPP_B_1', 'GPP_B_2', 'GPP_B_3', 'GPP_B_4', 'GPP_B_5', 'GPP_B_6', 'GPP_B_7', 'GPP_B_8', 'GPP_B_9', 'GPP_B_10', 'GPP_B_11', 'GPP_B_12', 'GPP_B_13', 'GPP_B_14', 'GPP_B_15', 'GPP_B_16', 'GPP_B_17', 'GPP_B_18', 'GPP_B_19', 'GPP_B_20', 'GPP_B_21', 'GPP_B_22', 'GPP_B_23', 'GPP_C_0', 'GPP_C_1', 'GPP_C_2', 'GPP_C_3', 'GPP_C_4', 'GPP_C_5', 'GPP_C_6', 'GPP_C_7', 'GPP_C_8', 'GPP_C_9', 'GPP_C_10', 'GPP_C_11', 'GPP_C_12', 'GPP_C_13', 'GPP_C_14', 'GPP_C_15', 'GPP_C_16', 'GPP_C_17', 'GPP_C_18', 'GPP_C_19', 'GPP_C_20', 'GPP_C_21', 'GPP_C_22', 'GPP_C_23', 'GPP_D_4', 'GPP_D_5', 'GPP_D_6', 'GPP_D_7', 'GPP_D_8', 'GPP_D_9', 'GPP_D_10', 'GPP_D_11', 'GPP_D_12', 'GPP_D_13', 'GPP_D_14', 'GPP_D_15', 'GPP_D_16', 'GPP_D_17', 'GPP_D_18', 'GPP_D_19', 'GPP_D_20', 'GPP_D_23', 'GPP_E_0', 'GPP_E_1', 'GPP_E_2', 'GPP_E_3', 'GPP_E_4', 'GPP_E_5', 'GPP_E_6', 'GPP_E_7', 'GPP_E_8', 'GPP_E_9', 'GPP_E_10', 'GPP_E_11', 'GPP_E_12', 'GPP_E_13', 'GPP_E_14', 'GPP_E_15', 'GPP_E_16', 'GPP_E_17', 'GPP_E_18', 'GPP_E_19', 'GPP_E_20', 'GPP_E_21', 'GPP_E_22', 'GPP_E_23', 'GPP_F_0', 'GPP_F_1', 'GPP_F_2', 'GPP_F_3', 'GPP_F_4', 'GPP_F_5', 'GPP_F_6', 'GPP_F_7', 'GPP_F_8', 'GPP_F_9', 'GPP_F_10', 'GPP_F_11', 'GPP_F_12', 'GPP_F_13', 'GPP_F_14', 'GPP_F_15', 'GPP_F_16', 'GPP_F_17', 'GPP_F_18', 'GPP_F_19', 'GPP_F_20', 'GPP_F_21', 'GPP_F_22', 'GPP_F_23', 'GPP_G_0', 'GPP_G_1', 'GPP_G_2', 'GPP_G_3', 'GPP_G_4', 'GPP_G_5', 'GPP_G_6', 'GPP_G_7', 'GPP_H_0', 'GPP_H_1', 'GPP_H_2', 'GPP_H_3', 'GPP_H_4', 'GPP_H_5', 'GPP_H_6', 'GPP_H_7', 'GPP_H_8', 'GPP_H_9', 'GPP_H_10', 'GPP_H_11', 'GPP_H_12', 'GPP_H_13', 'GPP_H_14', 'GPP_H_15', 'GPP_H_16', 'GPP_H_17', 'GPP_H_18', 'GPP_H_19', 'GPP_H_20', 'GPP_H_21', 'GPP_H_22', 'GPP_H_23', 'GPD_0', 'GPD_1', 'GPD_2', 'GPD_3', 'GPD_4', 'GPD_5', 'GPD_6', 'GPD_7', 'GPD_8', 'GPD_9', 'GPD_10', 'GPD_11']" label="Camera privacy GPIO Pin" help_text="This defines which GPIO is used to provide the current privacy state to the camera device. It is only applicable when the Camera Privacy feature NVAR is enabled" key="CsePlugin:CameraGpioNvar:Camera_Gpio"/>
</CameraPins>
</Gpio>
<Dnx label="Dnx">
<OEMandPlatformIDs label="DnX Fuses">
<DnxEnabled value="Yes" value_list="['Yes', 'No']" label="DnX Enabled" help_text="DnX permanent enable/disable FPF" key="CsePlugin:UEP:DnxEnabled"/>
<OemPlatformId value="0x0" label="OEM Platform ID" help_text="This setting allows OEMs to configure a Unique Platform ID into the base FPFs. Note: The OEM Platform ID FPF and Platform ID for the DnX Image should match." key="CsePlugin:UEP:OemPlatformId"/>
</OEMandPlatformIDs>
</Dnx>
<IntelUniquePlatformId label="Intel(R) Unique Platform ID">
<IntelUniquePlatformIdConfiguration label="Intel(R) Unique Platform ID Configuration">
<UniquePlatformId value="0x0" label="OEM ID" help_text="This setting allows OEMs to configure their PCIe Vendor ID Unique ID into the platform FPFs." key="CsePlugin:UEP:UniquePlatformId"/>
</IntelUniquePlatformIdConfiguration>
<EntitlementsConfiguration label="Entitlements Configuration">
<IcpsSwSkuing value="No" value_list="['No', 'Yes']" label="Intel(R) ICPS SW SKUing Eligible" help_text="Set to enabled when Intel Connectivity Performance Suite is licensed on this platform" key="CsePlugin:AutoNvars:icps#icpsSwSkuing"/>
</EntitlementsConfiguration>
</IntelUniquePlatformId>
<FWUpdate label="FWUpdate">
<FWUpdateImage label="FW Update Image Build">
<OEM_KM_enabled value="Enabled" value_list="['Disabled', 'Enabled']" label="OEM_KM Enabled" help_text="This setting Enables / Disables OEM_KM in the FWUpdate image." key="CsePlugin:OEM_KM:Enabled"/>
<IOM_enabled value="Enabled" value_list="['Disabled', 'Enabled']" label="IOM Enabled" help_text="This setting Enables / Disables IOM in the FWUpdate image." key="CsePlugin:IOM:Enabled"/>
<NPHY_enabled value="Enabled" value_list="['Disabled', 'Enabled']" label="NPHY Enabled" help_text="This setting Enables / Disables NPHY in the FWUpdate image." key="CsePlugin:NPHY:Enabled"/>
<TBT_enabled value="Enabled" value_list="['Disabled', 'Enabled']" label="TBT Enabled" help_text="This setting Enables / Disables TBT in the FWUpdate image." key="CsePlugin:TBT:Enabled"/>
<ISH_enabled value="Enabled" value_list="['Disabled', 'Enabled']" label="ISH Enabled" help_text="This setting Enables / Disables ISH in the FWUpdate image." key="CsePlugin:ISH:Enabled"/>
<IUnit_enabled value="Enabled" value_list="['Disabled', 'Enabled']" label="IUnit Enabled" help_text="This setting Enables / Disables IUnit in the FWUpdate image." key="CsePlugin:IUNIT:Enabled"/>
<GBST_enabled value="Enabled" value_list="['Disabled', 'Enabled']" label="GBST Enabled" help_text="This setting Enables / Disables GBST in the FWUpdate image." key="CsePlugin:GBST:Enabled"/>
</FWUpdateImage>
</FWUpdate>
</FitData>
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