570 lines
23 KiB
Plaintext
570 lines
23 KiB
Plaintext
## @file
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# File to declare variable default information
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#
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#******************************************************************************
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#* Copyright (c) 2018 - 2021, Insyde Software Corporation. All Rights Reserved.
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#*
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#* You may not reproduce, distribute, publish, display, perform, modify, adapt,
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#* transmit, broadcast, present, recite, release, license or otherwise exploit
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#* any part of this publication in any form, by any means, without the prior
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#* written permission of Insyde Software Corporation.
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#*
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#******************************************************************************
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#
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# This file is ini format and Comments are prefixed with a # and continue to the end of the line.
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#
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!include InsydeModulePkg/Package.var
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!include AlderLakeChipsetPkg/Package.var
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#_Start_L05_FEATURE_
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!include InsydeL05PlatformPkg/Package.var
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#_End_L05_FEATURE_
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#
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# Optional [Guids] section. uses to declare guid which used in this file.
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#
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[Guids]
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gSetupVariableGuid = {0xEC87D643, 0xEBA4, 0x4BB5, {0xA1, 0xE5, 0x3F, 0x3E, 0x36, 0xB2, 0x0D, 0xA9}}
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gSaSetupVariableGuid = {0x72c5e28c, 0x7783, 0x43a1, {0x87, 0x67, 0xfa, 0xd7, 0x3f, 0xcc, 0xaf, 0xa4}}
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gCpuSetupVariableGuid = {0xb08f97ff, 0xe6e8, 0x4193, {0xa9, 0x97, 0x5e, 0x9e, 0x9b, 0xa, 0xdb, 0x32}}
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gPchSetupVariableGuid = {0x4570b7f1, 0xade8, 0x4943, {0x8d, 0xc3, 0x40, 0x64, 0x72, 0x84, 0x23, 0x84}}
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gMeSetupVariableGuid = {0x5432122d, 0xd034, 0x49d2, {0xa6, 0xde, 0x65, 0xa8, 0x29, 0xeb, 0x4c, 0x74}}
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gSiSetupVariableGuid = {0xAAF8E719, 0x48F8, 0x4099, {0xA6, 0xF7, 0x64, 0x5F, 0xBD, 0x69, 0x4C, 0x3D}}
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gSystemConfigurationGuid = {0xA04A27f4, 0xDF00, 0x4D42, {0xB5, 0x52, 0x39, 0x51, 0x13, 0x02, 0x11, 0x3D}}
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#
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# The [Packages] section lists all of the package declaration files that contain
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# GUIDs or PCDs that are used by this variable declaration file.
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#
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[Packages]
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AlderLakeChipsetPkg/AlderLakeChipsetPkg.dec
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InsydeModulePkg/InsydeModulePkg.dec
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#
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# Below can write Var section to introduce a single UEFI variable default value for the specified
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# default stores and specified SKU.
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#
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# Section format is [Var.VariableGUID.VariableName] for example [Var.gEfiFileInfoGuid.MyTestVar]
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#
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###########################################################################
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# The default setting is come from
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# 1. Intel\AlderLake\AlderLakeBoardPkg\AlderLake"X"Boards\Include\AlderLake"X"BoardConfigPatchTable.h
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# Note: "X" means "U", "Y" or "H" SKU
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# 2. Command "cond" in Intel RC *.hfr file
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# 3. Variable which without default value
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# The Variable Offset defined in file AdvanceVfr.lst(build folder)
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#--------------------------------------------------------------------------
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# 0x3F|BoardIdAdlPSimics
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# 0x10|BoardIdAdlPLp4Rvp
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# 0x12|BoardIdAdlPDdr5Rvp
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# 0x13|BoardIdAdlPLp5Rvp
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# 0x19|BoardIdAdlPLp4Bep
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# 0x1A|BoardIdAdlPLp5Aep
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# 0x1E|BoardIdAdlPDdr5Dg02384Aep
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# 0x14|SkuIdAdlPDdr4Rvp
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# 0x00|BoardDefault
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[Var.gSetupVariableGuid.Setup]
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Attribs = BS | RT
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DefaultId = 0
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SkuId = 0
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Struct = SETUP_DATA
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Data = name=Rtd3Support | (1)
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name=StorageRtd3Support | (2)
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[Var.gSetupVariableGuid.Setup]
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Attribs = BS | RT
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DefaultId = 0
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SkuId = 0x3F,0x10,0x12,0x13,0x19,0x1A,0x1E,0x14
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Struct = SETUP_DATA
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Data = name=PchI2cSensorDevicePort[0] | (3)
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name=AuxOriOverrideSupport | (0)
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name=DiscreteTbtPlatformConfigurationSupport | (0)
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name=AcpiDebug | (1)
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name=ITbtRtd3 | (0)
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name=DisableTbtPcieTreeBme | (0)
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[Var.gSaSetupVariableGuid.SaSetup]
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Attribs = BS | RT
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DefaultId = 0
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SkuId = 0x3F,0x10,0x12,0x13,0x19,0x1A,0x1E,0x14
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Struct = SA_SETUP
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Data = name=EnableVtd | (0)
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name=PcieRootPortL1SubStates[1] | (0)
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name=PcieRootPortClockReqMsgEnable[1] | (0)
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name=SkipCdClockInit | (1)
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name=D3ColdEnable | (0)
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[Var.gCpuSetupVariableGuid.CpuSetup]
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Attribs = BS | RT
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DefaultId = 0
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SkuId = 0x3F,0x10,0x12,0x13,0x19,0x1A,0x1E,0x14
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Struct = CPU_SETUP
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Data = name=TmeEnable | (0)
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name=EnergyEfficientTurbo | (1)
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name=EnableGv | (0)
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name=PkgCStateLimit | (3)
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[Var.gPchSetupVariableGuid.PchSetup]
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Attribs = BS | RT
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DefaultId = 0
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SkuId = 0x3F,0x10,0x12,0x13,0x19,0x1A,0x1E,0x14
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Struct = PCH_SETUP
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Data = name=PchSerialIoSpi[1] | (1)
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name=PchUartHwFlowCtrl[0] | (0)
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name=PchSerialIoI2c[0] | (1)
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name=PchSerialIoI2c[1] | (1)
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name=PchSerialIoI2c[2] | (0)
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name=PchSerialIoI2c[3] | (0)
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name=PchSerialIoI2c[4] | (0)
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name=PchSerialIoI2c[5] | (1)
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name=PchIshGpEnable[7] | (1)
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#--------------------------------------------------------------------------
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# 0x03|SkuIdAdlS
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# 0x21|BoardIdAdlSTgpHDdr4SODimm1DCrb
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# 0x27|BoardIdAdlSAdpSDdr4UDimm2DCrb
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# 0x2B|BoardIdAdlSAdpSDdr5UDimm1DCrb
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# 0x2E|BoardIdAdlSAdpSDdr5UDimm2DCrb
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# 0x127|SkuIdAdlSAdpSDdr4UDimm2DCrbFab2
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# 0x12B|SkuIdAdlSAdpSDdr5UDimm1DCrbFab2
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# 0x30|BoardIdAdlSAdpSDdr5SODimmCrb
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# 0x35|BoardIdAdlSAdpSDdr4SODimmCrb
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# 0x33|BoardIdAdlSAdpSDdr5UDimm1DAep
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# 0x36|BoardIdAdlSAdpSDdr5UDimm1DOc
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[Var.gSetupVariableGuid.Setup]
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Attribs = BS | RT
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DefaultId = 0
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SkuId = 0x03,0x21,0x27,0x2B,0x2E,0x127,0x12B,0x30,0x35,0x36
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Struct = SETUP_DATA
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Data = name=TbtLegacyModeSupport | (0)
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name=AuxOriOverrideSupport | (0)
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name=HebcValueSupport | (1)
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name=PchI2cSensorDevicePort[0] | (1)
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name=PchI2cSensorDevicePort[1] | (2)
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name=PchSpiSensorDevicePort[1] | (1)
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name=NativeAspmEnable | (0)
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name=PepGfx | (1)
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name=PepPeg0 | (1)
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name=PepSataEnumeration | (1)
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name=PepI2c0 | (1)
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name=PepI2c1 | (1)
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name=PepI2c2 | (1)
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name=PepI2c3 | (1)
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name=PepI2c4 | (1)
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name=PepI2c5 | (1)
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name=PepSpi | (1)
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name=PepXhci | (1)
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name=PepAudio | (1)
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name=SysFwUpdateSkipPowerCheck | (1)
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name=TbtSetupFormSupport | (1)
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name=PepCsme | (1)
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name=PepGbe | (1)
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name=PepTcss | (1)
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name=EnableDptf | (0)
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name=MipiCam_ControlLogic0 | (0)
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name=MipiCam_ControlLogic1 | (0)
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name=MipiCam_ControlLogic2 | (0)
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name=MipiCam_ControlLogic3 | (0)
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name=MipiCam_ControlLogic4 | (0)
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name=MipiCam_ControlLogic5 | (0)
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name=MipiCam_Link0 | (0)
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name=MipiCam_Link1 | (0)
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name=MipiCam_Link2 | (0)
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name=MipiCam_Link3 | (0)
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name=MipiCam_Link4 | (0)
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name=MipiCam_Link5 | (0)
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name=PchI2cSensorDevicePort[2] | (4)
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name=TcssUcmDevice | (2)
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name=DiscreteTbtPlatformConfigurationSupport | (1)
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name=EcPeciModeUnsupport | (1)
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[Var.gSaSetupVariableGuid.SaSetup]
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Attribs = BS | RT
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DefaultId = 0
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SkuId = 0x03,0x21,0x27,0x2B,0x2E,0x33,0x127,0x12B,0x30,0x35,0x36
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Struct = SA_SETUP
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Data = name=TcssXhciEn | (0)
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[Var.gPchSetupVariableGuid.PchSetup]
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Attribs = BS | RT
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DefaultId = 0
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SkuId = 0x03,0x21,0x27,0x2B,0x2E,0x33,0x127,0x12B,0x36
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Struct = PCH_SETUP
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Data = name=PxDevSlp[0] | (1)
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name=PxDevSlp[1] | (1)
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name=PchSerialIoSpi[0] | (0)
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name=PchSerialIoSpi[1] | (1)
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name=PchSerialIoSpi[2] | (0)
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name=PchSerialIoUart[0] | (0)
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name=PchSerialIoUart[1] | (0)
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name=PchUartHwFlowCtrl[2] | (0)
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name=PchSerialIoI2c[2] | (1)
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name=PchSerialIoI2c[3] | (1)
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name=PchSerialIoI2c[4] | (1)
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name=PchSerialIoI2c[5] | (1)
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name=PchHdAudioI2sCodecSelect | (0)
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[Var.gSystemConfigurationGuid.Setup]
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Attribs = BS | RT
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DefaultId = 0
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SkuId = 0x2B
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Struct = CHIPSET_CONFIGURATION
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Data = name=HgSlot | (1)
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#--------------------------------------------------------------------------
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# 0x33|BoardIdAdlSAdpSDdr5UDimm1DAep
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[Var.gSetupVariableGuid.Setup]
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Attribs = BS | RT
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DefaultId = 0
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SkuId = 0x33
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Struct = SETUP_DATA
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Data = name=TbtLegacyModeSupport | (0)
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name=AuxOriOverrideSupport | (0)
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name=HebcValueSupport | (1)
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name=PchI2cSensorDevicePort[0] | (1)
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name=PchI2cSensorDevicePort[1] | (2)
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name=PchSpiSensorDevicePort[1] | (1)
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name=NativeAspmEnable | (0)
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name=PepGfx | (1)
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name=PepGna | (0)
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name=PepPeg0 | (1)
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name=PepSataEnumeration | (1)
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name=PepI2c0 | (1)
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name=PepI2c1 | (1)
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name=PepI2c2 | (1)
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name=PepI2c3 | (1)
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name=PepI2c4 | (1)
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name=PepI2c5 | (1)
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name=PepSpi | (1)
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name=PepXhci | (1)
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name=PepAudio | (1)
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name=SysFwUpdateSkipPowerCheck | (1)
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name=TbtSetupFormSupport | (1)
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name=PepCsme | (1)
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name=PepGbe | (1)
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name=PepTcss | (1)
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name=EnableDptf | (0)
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name=MipiCam_ControlLogic0 | (0)
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name=MipiCam_ControlLogic1 | (0)
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name=MipiCam_ControlLogic2 | (0)
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name=MipiCam_ControlLogic3 | (0)
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name=MipiCam_ControlLogic4 | (0)
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name=MipiCam_ControlLogic5 | (0)
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name=MipiCam_Link0 | (0)
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name=MipiCam_Link1 | (0)
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name=MipiCam_Link2 | (0)
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name=MipiCam_Link3 | (0)
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name=MipiCam_Link4 | (0)
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name=MipiCam_Link5 | (0)
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name=AdlSAepBoard | (1)
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name=DiscreteTbtPlatformConfigurationSupport | (1)
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#--------------------------------------------------------------------------
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# 0x30|BoardIdAdlSAdpSDdr5SODimmCrb
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# 0x35|BoardIdAdlSAdpSDdr4SODimmCrb
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[Var.gPchSetupVariableGuid.PchSetup]
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Attribs = BS | RT
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DefaultId = 0
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SkuId = 0x30,0x35
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Struct = PCH_SETUP
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Data = name=PxDevSlp[0] | (1)
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name=PxDevSlp[1] | (1)
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name=PchSerialIoSpi[0] | (0)
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name=PchSerialIoSpi[1] | (1)
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name=PchSerialIoSpi[2] | (0)
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name=PchSerialIoUart[0] | (0)
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name=PchSerialIoUart[1] | (0)
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name=PchUartHwFlowCtrl[2] | (0)
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name=PchSerialIoI2c[2] | (1)
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name=PchSerialIoI2c[3] | (1)
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name=PchSerialIoI2c[4] | (1)
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name=PchSerialIoI2c[5] | (1)
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name=PchHdAudioI2sCodecSelect | (0)
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name=PchLan | (0)
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name=FoxvilleLanSupport | (1)
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name=FoxvilleWakeOnLan | (1)
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#--------------------------------------------------------------------------
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# 0x36|BoardIdAdlSAdpSDdr5UDimm1DOc
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[Var.gPchSetupVariableGuid.PchSetup]
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Attribs = BS | RT
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DefaultId = 0
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SkuId = 0x36
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Struct = SI_SETUP
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Data = name=PlatformDebugConsent | (2)
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[Var.gSystemConfigurationGuid.Setup]
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Attribs = BS | RT
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DefaultId = 0
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SkuId = 0
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Struct = KERNEL_CONFIGURATION
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Data = name=AcpiVer | (7)
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#--------------------------------------------------------------------------
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# 0x3A|BoardIdAdlSAdpSSbgaDdr5SODimmErb
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# 0x3B|BoardIdAdlSAdpSSbgaDdr5SODimmCrb
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# 0x2F|BoardIdAdlSAdpSSbgaDdr5SODimmAep
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[Var.gSetupVariableGuid.Setup]
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Attribs = BS | RT
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DefaultId = 0
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SkuId = 0x3A,0x3B
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Struct = SETUP_DATA
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Data = name=TbtLegacyModeSupport | (0)
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name=AuxOriOverrideSupport | (0)
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name=HebcValueSupport | (1)
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name=PchI2cSensorDevicePort[0] | (1)
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name=PchI2cSensorDevicePort[1] | (2)
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name=PchI2cSensorDevicePort[3] | (2)
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name=NativeAspmEnable | (0)
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name=PepGfx | (1)
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name=PepPeg0 | (1)
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name=PepSataEnumeration | (1)
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name=PepI2c0 | (1)
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name=PepI2c1 | (1)
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name=PepI2c2 | (1)
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name=PepI2c3 | (1)
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name=PepI2c4 | (1)
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name=PepI2c5 | (1)
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name=PepSpi | (1)
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name=PepXhci | (1)
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name=PepAudio | (1)
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name=SysFwUpdateSkipPowerCheck | (1)
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name=TbtSetupFormSupport | (1)
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name=PepCsme | (1)
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name=PepGbe | (1)
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name=PepTcss | (1)
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name=EnableDptf | (0)
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name=MipiCam_ControlLogic0 | (0)
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name=MipiCam_ControlLogic1 | (0)
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name=MipiCam_ControlLogic2 | (0)
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name=MipiCam_ControlLogic3 | (0)
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name=MipiCam_ControlLogic4 | (0)
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name=MipiCam_ControlLogic5 | (0)
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name=MipiCam_Link0 | (0)
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name=MipiCam_Link1 | (0)
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name=MipiCam_Link2 | (0)
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name=MipiCam_Link3 | (0)
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name=MipiCam_Link4 | (0)
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name=MipiCam_Link5 | (0)
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name=DiscreteTbtPlatformConfigurationSupport | (1)
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name=DiscreteTbtSupport | (1)
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name=DTbtRtd3ClkReq | (1)
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name=DTbtController[0] | (1)
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name=DTbtController[1] | (1)
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name=DTbtRtd3 | (1)
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name=ITbtRootPort[0] | (0)
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name=ITbtRootPort[1] | (0)
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name=ITbtRootPort[2] | (0)
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name=ITbtRootPort[3] | (0)
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[Var.gSaSetupVariableGuid.SaSetup]
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Attribs = BS | RT
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DefaultId = 0
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SkuId = 0x3A,0x3B,0x2F
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Struct = SA_SETUP
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Data = name=TcssXhciEn | (0)
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Data = name=MaxTolud | (0)
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[Var.gCpuSetupVariableGuid.CpuSetup]
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Attribs = BS | RT
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DefaultId = 0
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SkuId = 0x3A,0x3B,0x2F
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Struct = CPU_SETUP
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Data = name=Irms | (1)
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[Var.gPchSetupVariableGuid.PchSetup]
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Attribs = BS | RT
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DefaultId = 0
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SkuId = 0x3A,0x3B
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Struct = PCH_SETUP
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Data = name=PxDevSlp[0] | (1)
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name=PxDevSlp[1] | (1)
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name=PchSerialIoSpi[0] | (0)
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name=PchSerialIoSpi[1] | (1)
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name=PchSerialIoSpi[2] | (0)
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name=PchSerialIoUart[0] | (0)
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name=PchSerialIoUart[1] | (0)
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name=PchUartHwFlowCtrl[2] | (0)
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name=PchSerialIoI2c[2] | (1)
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name=PchSerialIoI2c[3] | (1)
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name=PchSerialIoI2c[4] | (1)
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name=PchSerialIoI2c[5] | (1)
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name=PchHdAudioI2sCodecSelect | (0)
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name=PchLan | (0)
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name=PcieRootPortHPE[8] | (1)
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name=PcieRootPortHPE[24] | (1)
|
|
name=PsOnEnable | (0)
|
|
name=FoxvilleLanSupport | (1)
|
|
name=FoxvilleWakeOnLan | (1)
|
|
|
|
#--------------------------------------------------------------------------
|
|
# 0x2F|BoardIdAdlSAdpSSbgaDdr5SODimmAep
|
|
|
|
[Var.gSetupVariableGuid.Setup]
|
|
Attribs = BS | RT
|
|
DefaultId = 0
|
|
SkuId = 0x2F
|
|
Struct = SETUP_DATA
|
|
Data = name=TbtLegacyModeSupport | (0)
|
|
name=AuxOriOverrideSupport | (0)
|
|
name=HebcValueSupport | (1)
|
|
name=PchI2cSensorDevicePort[0] | (1)
|
|
name=PchI2cSensorDevicePort[1] | (2)
|
|
name=PchSpiSensorDevicePort[1] | (1)
|
|
name=NativeAspmEnable | (0)
|
|
name=PepGfx | (1)
|
|
name=PepPeg0 | (1)
|
|
name=PepSataEnumeration | (1)
|
|
name=PepI2c0 | (1)
|
|
name=PepI2c1 | (1)
|
|
name=PepI2c2 | (1)
|
|
name=PepI2c3 | (1)
|
|
name=PepI2c4 | (1)
|
|
name=PepI2c5 | (1)
|
|
name=PepSpi | (1)
|
|
name=PepXhci | (1)
|
|
name=PepAudio | (1)
|
|
name=SysFwUpdateSkipPowerCheck | (1)
|
|
name=TbtSetupFormSupport | (1)
|
|
name=PepCsme | (1)
|
|
name=PepGbe | (1)
|
|
name=PepTcss | (1)
|
|
name=EnableDptf | (0)
|
|
name=MipiCam_ControlLogic0 | (0)
|
|
name=MipiCam_ControlLogic1 | (0)
|
|
name=MipiCam_ControlLogic2 | (0)
|
|
name=MipiCam_ControlLogic3 | (0)
|
|
name=MipiCam_ControlLogic4 | (0)
|
|
name=MipiCam_ControlLogic5 | (0)
|
|
name=MipiCam_Link0 | (0)
|
|
name=MipiCam_Link1 | (0)
|
|
name=MipiCam_Link2 | (0)
|
|
name=MipiCam_Link3 | (0)
|
|
name=MipiCam_Link4 | (0)
|
|
name=MipiCam_Link5 | (0)
|
|
name=DiscreteTbtPlatformConfigurationSupport | (1)
|
|
name=DiscreteTbtSupport | (1)
|
|
name=DTbtRtd3ClkReq | (1)
|
|
name=DTbtController[0] | (1)
|
|
name=DTbtController[1] | (0)
|
|
name=DTbtRtd3 | (1)
|
|
|
|
[Var.gSaSetupVariableGuid.SaSetup]
|
|
Attribs = BS | RT
|
|
DefaultId = 0
|
|
SkuId = 0x2F
|
|
Struct = SA_SETUP
|
|
Data = name=PrimaryDisplay | (4)
|
|
|
|
[Var.gPchSetupVariableGuid.PchSetup]
|
|
Attribs = BS | RT
|
|
DefaultId = 0
|
|
SkuId = 0x2F
|
|
Struct = PCH_SETUP
|
|
Data = name=PxDevSlp[0] | (1)
|
|
name=PxDevSlp[1] | (1)
|
|
name=PchSerialIoSpi[0] | (0)
|
|
name=PchSerialIoSpi[1] | (1)
|
|
name=PchSerialIoSpi[2] | (0)
|
|
name=PchSerialIoUart[0] | (0)
|
|
name=PchSerialIoUart[1] | (0)
|
|
name=PchUartHwFlowCtrl[2] | (0)
|
|
name=PchSerialIoI2c[2] | (1)
|
|
name=PchSerialIoI2c[3] | (1)
|
|
name=PchSerialIoI2c[4] | (1)
|
|
name=PchSerialIoI2c[5] | (1)
|
|
name=PchHdAudioI2sCodecSelect | (0)
|
|
name=PchLan | (0)
|
|
name=PcieRootPortHPE[8] | (1)
|
|
name=PcieRootPortHPE[24] | (0)
|
|
name=PsOnEnable | (0)
|
|
name=FoxvilleLanSupport | (1)
|
|
name=FoxvilleWakeOnLan | (1)
|
|
|
|
#--------------------------------------------------------------------------
|
|
# 0x3E|BoardIdAdlSAdpSSbgaDdr4SODimmCrb
|
|
|
|
[Var.gSetupVariableGuid.Setup]
|
|
Attribs = BS | RT
|
|
DefaultId = 0
|
|
SkuId = 0x3E
|
|
Struct = SETUP_DATA
|
|
Data = name=TbtLegacyModeSupport | (0)
|
|
name=AuxOriOverrideSupport | (0)
|
|
name=HebcValueSupport | (1)
|
|
name=PchI2cSensorDevicePort[1] | (2)
|
|
name=PchI2cSensorDevicePort[3] | (2)
|
|
name=NativeAspmEnable | (0)
|
|
name=PepGfx | (1)
|
|
name=PepPeg0 | (1)
|
|
name=PepSataEnumeration | (1)
|
|
name=PepI2c0 | (1)
|
|
name=PepI2c1 | (1)
|
|
name=PepI2c2 | (1)
|
|
name=PepI2c3 | (1)
|
|
name=PepI2c4 | (1)
|
|
name=PepI2c5 | (1)
|
|
name=PepSpi | (1)
|
|
name=PepXhci | (1)
|
|
name=PepAudio | (1)
|
|
name=SysFwUpdateSkipPowerCheck | (1)
|
|
name=TbtSetupFormSupport | (1)
|
|
name=PepCsme | (1)
|
|
name=PepGbe | (1)
|
|
name=PepTcss | (1)
|
|
name=EnableDptf | (0)
|
|
name=MipiCam_ControlLogic0 | (0)
|
|
name=MipiCam_ControlLogic1 | (0)
|
|
name=MipiCam_ControlLogic2 | (0)
|
|
name=MipiCam_ControlLogic3 | (0)
|
|
name=MipiCam_ControlLogic4 | (0)
|
|
name=MipiCam_ControlLogic5 | (0)
|
|
name=MipiCam_Link0 | (0)
|
|
name=MipiCam_Link1 | (0)
|
|
name=MipiCam_Link2 | (0)
|
|
name=MipiCam_Link3 | (0)
|
|
name=MipiCam_Link4 | (0)
|
|
name=MipiCam_Link5 | (0)
|
|
name=DiscreteTbtPlatformConfigurationSupport | (1)
|
|
|
|
[Var.gSaSetupVariableGuid.SaSetup]
|
|
Attribs = BS | RT
|
|
DefaultId = 0
|
|
SkuId = 0x3E
|
|
Struct = SA_SETUP
|
|
Data = name=TcssXhciEn | (0)
|
|
|
|
[Var.gCpuSetupVariableGuid.CpuSetup]
|
|
Attribs = BS | RT
|
|
DefaultId = 0
|
|
SkuId = 0x3E
|
|
Struct = CPU_SETUP
|
|
Data = name=Irms | (1)
|
|
|
|
[Var.gPchSetupVariableGuid.PchSetup]
|
|
Attribs = BS | RT
|
|
DefaultId = 0
|
|
SkuId = 0x3E
|
|
Struct = PCH_SETUP
|
|
Data = name=PxDevSlp[0] | (1)
|
|
name=PxDevSlp[1] | (1)
|
|
name=PchSerialIoSpi[0] | (0)
|
|
name=PchSerialIoSpi[1] | (1)
|
|
name=PchSerialIoSpi[2] | (0)
|
|
name=PchSerialIoUart[0] | (0)
|
|
name=PchSerialIoUart[1] | (0)
|
|
name=PchUartHwFlowCtrl[2] | (0)
|
|
name=PchSerialIoI2c[2] | (1)
|
|
name=PchSerialIoI2c[3] | (1)
|
|
name=PchSerialIoI2c[4] | (1)
|
|
name=PchSerialIoI2c[5] | (1)
|
|
name=PchHdAudioI2sCodecSelect | (0)
|
|
name=PchLan | (0)
|
|
name=FoxvilleLanSupport | (1)
|
|
name=FoxvilleWakeOnLan | (1) |